Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2006-01-17
2006-01-17
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
Reexamination Certificate
active
06988188
ABSTRACT:
A structure for a data object is disclosed with a field and format structure optimized for use by a set of pipeline stages that are interconnected logically through a common pipeline memory. The data object includes both a first portion containing data relating to one or more of a plurality of parameters associated with the control and/or the configuration of one or more processing circuitry blocks, and a second portion containing data associated with computations performed by the processing circuitry blocks. Other portions contain both general and specific types of operational control information used by the processing circuitry blocks. The data object acts as a form of common data exchange mechanism between disparate types of pipeline stages, including in hybrid (mixed) software-hardware pipelines. The control data in the data object can be used by a first pipeline stage to affect or adaptively change operational functioning of downstream pipeline stages.
REFERENCES:
patent: 5115451 (1992-05-01), Furlong
patent: 5335508 (1994-10-01), Kan
patent: 5524244 (1996-06-01), Robinson et al.
patent: 5687325 (1997-11-01), Chang
patent: 5696759 (1997-12-01), Tomonaga et al.
patent: 5768598 (1998-06-01), Marisetty et al.
patent: 5909559 (1999-06-01), So
patent: 5920561 (1999-07-01), Daniel et al.
patent: 5920705 (1999-07-01), Lyon et al.
patent: 5933447 (1999-08-01), Tran et al.
patent: 5949762 (1999-09-01), Green et al.
patent: 6023753 (2000-02-01), Pechanek et al.
patent: 6081783 (2000-06-01), Divine et al.
patent: 6088785 (2000-07-01), Hudson et al.
patent: 6101592 (2000-08-01), Pechanek et al.
patent: 6131114 (2000-10-01), Guezou et al.
patent: 6151668 (2000-11-01), Pechanek et al.
patent: 6157051 (2000-12-01), Allsup et al.
patent: 6167501 (2000-12-01), Barry et al.
patent: 6167502 (2000-12-01), Pechanek et al.
patent: 6173389 (2001-01-01), Pechanek et al.
patent: 6182206 (2001-01-01), Baxter
patent: 6282238 (2001-08-01), Landry
patent: 6353854 (2002-03-01), Cromer et al.
patent: 6560648 (2003-05-01), Dunn et al.
patent: 6587476 (2003-07-01), Lewin et al.
patent: 6601101 (2003-07-01), Lee et al.
patent: 0010281 (2000-02-01), None
patent: 0010297 (2000-02-01), None
patent: 0019311 (2000-04-01), None
patent: 1059785 (2000-12-01), None
patent: 0113590 (2001-02-01), None
patent: 0124030 (2001-04-01), None
Kumar N. Ganapathy and Benjamin W. Wah,Designing a Coprocessor for Recurrent Computations, In Proceedings of the 5th IEEE Symposium on Distributed Processing, pp. 806-813, Dec. 1993.
J. G. Eldredge and B. L. Hutchings,Run-time reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs, Journal of VLSI Signal Processing, 17 pages, 1996.
M. J. Wirthlin and B. L. Hutchings,Sequencing run-time reconfigured hardware with software, In FPGA '96 1996 ACM Fourth International Symposium on Field Programmable Gate Arrays, pp. 122-128, New York, NY, Feb. 1996. ACM.
T. Miyamori and K. Olukotun,A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications, in Proc. IEEE Symp. on FPGAs for Custom Computing Machines, Napa Valley, California, 1998, pp. 2-11.
D. Scherrer and H. Eberle,A Scalable Real-time Signal Processor for Object-oriented Data Flow Applications, PDCS-98 11th Int. Conf. on Parallel and Distributed Computing Systems, Chicago, Sep. 2-4, 1998, pp. 183-189.
K. Compton and S. Hanck,Configurable Computing: A Survey of Systems and Software, Northwestern University, Dept. of ECE Technical Report, 1999, 39 pages.
H.J. Broersma, N. Bruin, J. L. Hurink, L.E.E Meester, S.S. op de Beek and J.H. Westhuis,Throughput of ADSL modems, Memorandum No. 1482, ISSN 0169-2690, pp. 1-17.
Paul Graham and Brent Nelson,Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing, in Proceedings of the Ninth International Workshop on Field Programmable Logic and Applications, Aug. 1999, 10 pages.
O. Diessel and G. Wigley,Opportunities for Operating Systems Research in Reconfigurable Computing, Technical report ACRC-99-018, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, Aug., 1999, pp. 1-12.
S. Köhler, S. Sawitzki, R. G. Spallek,Digital Signal Processors for Multimedia Applications, in Proceedings of the 4th World Multiconference on Systemics, Cybernetics and Informatics and the 6th International Conference on Information Systems, Analysis and Synthesis (SCI/ISAS 2000), vol. VI, Image Acoustic, Speech and Signal Processing: Part II, pp. 107-112, International Institute of Informatics an d Systemics, 2000.
Stephan Wong, Sorin Cotofans, Stamatis Vassiliadis,Multimedia Enhanced General-Processors, IEEE International Conference on Multimedia and Expo (III) 2000: 1496-1496.
Russell Tessier and Wayne Burleson,Reconfigurable Computing for Digital Signal Processing: A Survey, Department of Electrical and Computer Engineering, University of Massachusetts, Apr. 12, 2000, pp. 1-2.
Brian R. Wiese and Jacky S. Chow,Programmable Implementations of xDSL Transceiver Systems, IEEE Communications, May 2000, pp. 114-119.
Coleman Eric
Hsu Winston
Realtek Semiconductor Corp.
LandOfFree
Data object architecture and method for xDSL ASIC processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data object architecture and method for xDSL ASIC processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data object architecture and method for xDSL ASIC processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3538276