Data memory with short memory access time

Details Data memory with short memory access time Data memory with short memory access time

2002-09-23

2004-08-31

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06785170

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates to a data memory with a short access time, which has a main data memory and a redundancy data memory for the replacement of defective data memory units of the main data memory.
BACKGROUND
The size of data memories and the integration level of data memories are increasing more and more on account of the increased requirements particularly in the case of customized ASIC circuits. On account of the high integration level required and the large memory sizes required, in the course of the complex fabrication process, defective data memory units are also produced here and there in addition to the functioning data memory units. In order to find such defective memory cells, data memories, after they have been fabricated, are subjected to a memory test in which test data patterns are applied to the memory and then a check is made to determine whether the data read out correspond to an expected test data read-out pattern.
In order to prevent a few failed data memory units from rendering the entire data memory fabricated nonfunctional, increasingly redundant memory areas are additionally being provided in data memories, which memory areas serve for the replacement of defective data memory units. For this purpose, in a data memory organized in rows and columns, replacement memory rows and replacement memory columns are additionally incorporated on the data memory chip.
FIG. 1
diagrammatically shows the construction of a data memory with a redundant memory area according memory test, the test data pattern read out is firstly stored and the addresses of the defective data memory units of the data memory are determined by comparison with expected test output patterns. The defective addresses determined are programmed into the redundancy logic, so that, in the event of access to the address of a defective data memory unit within the data memory, a replacement data memory unit within the redundancy data memory is accessed. In order to test whether the address diversion within the redundancy logic has been ended successfully, in a subsequent further test step, by comparing test data patterns a check is made to determine whether the memory is now functional.
In the event of a memory access to the data memory, firstly an address comparison is effected in the redundancy logic and afterward, provided that the addressed data memory unit is not defective, the addressed data memory unit within the data memory is accessed or, if the addressed data memory unit is identified as a defective data memory unit, a replacement data memory unit within the redundant memory is accessed.
One disadvantage of the arrangement according to the prior art as illustrated in
FIG. 1
is that the redundant memory is integrated into the original data memory. In the case of a prescribed data memory with a predetermined size, for example a RAM memory with a memory space of one megabyte, the data memory must be correspondingly adapted in circuitry for the integration of a redundant memory space.
The memory illustrated in
FIG. 1
furthermore has the serious disadvantage that the memory access to a data memory unit takes a relatively long time. The memory access time T
access
to a data memory unit within the memory illustrated in
FIG. 1
is the sum of the address comparison time T
V
, required for the address comparison within the redundancy logic, and the access time to the data memory T
ZD
.
T
access
=T
ZD
+T
V
SUMMARY OF THE INVENTION
The object of the present invention is to provide a data memory with redundant memory which has the shortest possible memory access time.
This object is achieved according to the invention by means of a data memory in the features specified in patent claim
1
.
The invention provides a data memory having a main data memory comprising a multiplicity of data memory units, a redundancy data memory, which comprises a plurality of redundancy data memory units for the replacement of defective data memory units of the main data memory, and having a redundancy control logic for controlling the access to the redundancy data memory, the main data memory and the redundancy data memory being connected to a data bus in parallel with one another via data lines, and the main data memory and the redundancy control logic being connected, in parallel with one another, via address lines, to an address bus for the addressing of data memory units in the data memory.
One advantage of the data memory according to the invention is that it is provided with a redundant memory without the main data memory having to be adapted in circuitry.
A further advantage of the data memory having the features specified in patent claim
1
is the expedient nature of its testing, since the redundancy data memory can immediately be concomitantly tested when a test pattern is applied for checking the functionality of the data memory.
In a preferred embodiment of the data memory, the redundancy control logic has an address memory with a plurality of address memory units, which store addresses of defective data memory units of the main data memory.
In one embodiment of the data memory, the address memory units are associative memory units CAM connected to the address bus, the associative memory units being provided for enabling associated redundancy data memory units of the redundancy data memory.
In a further embodiment, the address memory units are address memory registers.
In this case, the address memory registers preferably each have a flag bit which indicates whether the content of the address memory register is valid.
The redundancy control logic preferably has a plurality of comparators which are in each case connected to an address memory register and the address bus and enable an associated redundancy data memory unit of the redundancy data memory if the address present in the address bus corresponds to the address stored in the address memory register.
The redundancy control logic preferably controls a first multiplexer for reading data from the main data memory or the redundancy data memory.
In a further preferred embodiment, the main data memory, the redundancy data memory and the redundancy control logic are connected, in parallel with one another, to a control bus for controlling the read or write access to the data memory.
In a particularly preferred embodiment of the data memory according to the invention, the address memory is connected to a programmed, non-erasable address read-only memory for permanently storing addresses of defective data memory units of the main data memory.
The redundancy control logic preferably controls a second multiplexer, which is connected, on the input side, to the redundancy data memory units of the redundancy memory and serves for reading data from one of the redundancy data memory units.
In this case, the redundancy data memory units of the redundancy memory are preferably data registers.
In a preferred embodiment, the main data memory is a RAM data memory.
In a further preferred embodiment, the main data memory is an SRAM data memory.
An address of a defective data memory unit of the main data memory can preferably be read out in an address memory unit of the address memory from a memory test logic integrated in the data memory, from an automatic test device or from the address read-only memory, and be written to the address memory unit.
Preferred embodiments of the data memory according to the invention are described below in order to elucidate features essential to the invention, with reference to the accompanying figures.


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Chen, Tom,A Self-Te

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