Data memory controller that supports data bus invert

Details Data memory controller that supports data bus invert Data memory controller that supports data bus invert

2008-04-08

2008-04-08

Lee, Christopher E. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S106000, C711S167000

Reexamination Certificate

active

07356632

ABSTRACT:
The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

REFERENCES:
patent: 6046943 (2000-04-01), Walker
patent: 6295246 (2001-09-01), Jeddeloh
Mircea R. Stan et al., “Bus-Invert Coding for Low-Power I/O” IEEE transactions on very Large Scale Integration (VLSI) Systems, vol. 3, No. 1, Mar. 1995, pp. 49-58.

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