Data memory circuit

Details Data memory circuit Data memory circuit

Filed on

2008-04-15

Date issued

2008-04-15

Examiner

Portka, Gary (Department: 2188)

Patent Class

Electrical computers and digital processing systems: memory

SubClass

Storage accessing and control

SubSubClass

Control technique

Other Related Categories

C711S167000, C365S222000, C710S005000

Type

Reexamination Certificate

Status

active

Patent number

10817504

Description

ABSTRACT:
A data memory circuit is provided. In one embodiment, the data memory circuit comprises a plurality of addressable memory cells, a command decoding device for decoding external commands and a control device for controlling or initiating operations for the operation of the data memory circuit in each case in a manner dependent on the decoded commands. The memory circuit has critical operating states in which the execution of specific commands is impermissible resulting in the course of specific operations in the data memory circuit, wherein a command buffer device buffer-stores commands received during the duration of their impermissibility and releases them for execution after the end of their impermissibility.

REFERENCES:
patent: 6377509 (2002-04-01), Yagishita
patent: 6385691 (2002-05-01), Mullarkey et al.
patent: 6404689 (2002-06-01), Kirihata et al.
patent: 6898683 (2005-05-01), Nakamura
patent: 2002/0145930 (2002-10-01), Bando
German Examination Report dated Jan. 29, 2004.

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