Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-04-10
2007-04-10
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S126000, C711S143000
Reexamination Certificate
active
10802930
ABSTRACT:
A data memory cache unit is provided which is capable of heightening the speed of memory access. The cache unit117executes reading and writing of data in a 16-byte width line unit in a main memory unit131, executes reading and writing of data in an MPU113in the unit of a four-byte width small area included in each line. When the MPU113executes a push instruction, if a cache miss takes place on a line which includes a small area that holds data which should be read out to the MPU113(NO at S1), then the cache unit117opens the line (S301). If a small area into which the data sent from the MPU113should be written is adjacent to a line boundary on the side where an address is larger or on the side where write-in is earlier executed (YES at S56), then the cache unit117does not execute a refill, and if this small area is not adjacent to the line boundary (NO at S56), then it executes a refill (S21).
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Matsushita Electric - Industrial Co., Ltd.
Peugh Brian R.
Wenderoth , Lind & Ponack, L.L.P.
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