Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-07-13
2001-03-06
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C713S100000
Reexamination Certificate
active
06199150
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data memory apparatus including at least one memory device forming a memory map which includes a plurality of memory areas.
2. Description of the Related Art
FIG. 11
shows a structure of a conventional data memory apparatus
300
. The data memory apparatus
300
includes memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
and a controller
140
for controlling the memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
. The memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
and the controller
140
are connected to one another through a conductive line
120
. Data is read from or written to the memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
by access from the controller
140
.
The controller
140
in the data memory apparatus
300
is connected to a processor
130
.
The data memory apparatus
300
having such a structure is in wide use for computers and consumer electronic appliances. The data memory apparatus
300
stores various data such as programs so that the processor
130
can execute any specified software.
FIG. 12
shows a structure of a memory map in the data memory apparatus
300
. The memory map has a memory area of 9 megabytes (8 megabyte RAM area+1 megabyte VIDEO/ROM area). The VIDEO/ROM area is a memory area for VIDEO RAM and system ROM. The memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
are each assigned to a one-megabyte RAM area.
Recently, higher-speed and more complicated processing has been demanded by users. In order to comply with these demands, a large volume of data need be read from and written into the memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
. Therefore, the data transfer speed required between the controller
140
(
FIG. 11
) and the memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
has been increased remarkably.
However, the controller
140
and the memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
are usually connected to each other on a PC substrate or a silicon substrate through conductive line
120
formed of copper or aluminum. When the signal frequency is increased to raise the data transfer speed, the signal is disrupted by reflections or the like generated at input ends of the controller
140
and the memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
. In order to avoid such disturbance of the signal, conductive line
120
needs to be shortened as the signal frequency is increased.
When conductive line
120
is shortened, the number of memory devices which can be connected to conductive line
120
is reduced. As a result, memory capacity is reduced. This is contrary to the current demand for processing a large volume of data.
Among various types of processing demanded by the users, some types, such as image processing, are complicated and require frequent memory access; and some types, such as wordprocessing, are relatively simple and require less frequent memory access. However, conventionally, different types of data (including programs) which are accessed at significantly different frequencies (i.e., the number of times a type of data is accessed) are mapped uniformly in each area of the memory map. The structure shown in
FIG. 12
is of such a conventional memory map which is flat in terms of speed.
One conventional method for increasing the memory access speed utilizes a cache memory
150
(FIG.
11
), which is provided in the processor
130
. By this method, however, a part of the data in the memory map, which is flat in terms of speed, is merely copied into the cache memory
150
. When a cache hit miss occurs, the memory devices
102
,
104
,
106
,
108
,
110
,
112
,
114
and
116
, which are equal in terms of speed, are accessed.
SUMMARY OF THE INVENTION
As used herein, the term “data” represents a concept including data and program.
A data memory apparatus according to the present invention includes at least one memory device forming a memory map including at least a first memory area and a second memory area; and an access control unit for controlling access to the at least one memory device so that an access speed to the first memory area is different from an access speed to the second memory area.
According to such a structure, the memory map can have a hierarchical structure in accordance with the access speed. Thus, the memory access can be optimized. For example, data required to be accessed at a high speed (for example, data accessed frequently) can be stored in a high-speed memory area; and data which can be accessed at a low speed (for example, data accessed less frequently) can be stored in a low-speed memory area. By optimizing the memory access in this manner, the performance of the entire system including the processor and the data memory apparatus is improved. Therefore, the memory capacity is increased without sacrificing the performance of the entire system.
In one embodiment of the invention, the memory map includes at least a high-speed memory device and a low-speed memory device. The memory device operates at a higher speed than the low-speed memory device. The high-speed memory device is assigned to the first memory area, and the low-speed memory device is assigned to the second memory area.
As a high-speed memory device, a high-speed and expensive memory (e.g., an SRAM) is used. As a low-speed memory device, a low-speed and inexpensive memory (e.g., a DRAM) is used. Thus, the memory devices forming the memory map can be optimized.
In one embodiment of the invention, the access control unit is connected to the high-speed memory device through a first bus and connected to the low-speed memory bus through a second bus.
In such a bus structure, data transferred at different speeds is not on the same bus. Thus, data conflict is avoided relatively easily, and control of data input and output is performed by the access control unit relatively easily.
In one embodiment of the invention, the access control unit includes a controller for inputting data to and outputting data from the first bus; and a transceiver for converting a transfer speed of data on the first bus and placing the data on the first bus onto the second bus at the converted transfer speed.
In such a structure, the controller is required to have only a port for the first bus. Therefore, any commercially available one-port controller is usable.
In one embodiment of the invention, the first bus is shorter than the second bus.
By setting the length of the first bus to be less than the length of the second bus, signal reflections which inadvantageously occurs at an input end of a high-speed memory device are restricted. By setting the length of the second bus to be greater than the length of the first bus, more memory devices can be connected to the second bus than to the first bus. Thus, memory capacity is increased.
In one embodiment of the invention, the transceiver includes a first-in-first-out buffer for storing the data on the first bus.
In such a structure, data on the first bus is stored in the first-in-first-out buffer temporarily. Therefore, the data on the first bus can be transferred at a high speed.
In one embodiment of the invention, the controller outputs a control signal to the transceiver, and the transceiver converts the transfer speed of the data on the first bus in accordance with the control signal.
In such a structure, the controller can control data input to and data output from the transceiver at desired timing. Thus, the utilization efficiency of both the first bus and the second bus is improved.
In one embodiment of the invention, the second bus is connected to a connector for providing an additional low-speed memory device.
In such a structure, an additional low-speed memory device can be provided by inserting a module card including a low-speed memory device into the connector. Since the connector is connected to the second b
Matsushita Electric - Industrial Co., Ltd.
Portka Gary J.
Renner , Otto, Boisselle & Sklar, LLP
Yoo Do Hyun
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