Data memory

Details Data memory Data memory

1999-11-22

2003-01-14

Iqbal, Nadeem (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C365S201000

Reexamination Certificate

active

06507917

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a data memory, and more particularly to a data memory with a RAM or ROM that includes a redundancy circuit.
BACKGROUND OF THE INVENTION
Data memories, such as those that can include a random access memory (RAM) or read only memory (ROM) are currently prevalent in many types of electronic devices. Increasingly, it is desirable to increase the capacity and/or degree of integration in such data memories.
While data memories continue to increase in size, it can be difficult to fabricate high capacity, high integration data memories that are always defect free. In order to increase the manufacturing yield of data memories, data memories typically include one or more spare memory cells.
Data memories can often be fabricated as integrated circuits in a substrate material, such as a semiconductor. As just one example, a data memory may be one of many “dies” in a “wafer.” A die may be subsequently “packaged.” Data memories are typically tested, prior to packaging, for defective memory cells. In the event a defective memory cell is detected, the defective memory cell may be replaced by a spare memory cell. As just one example, address data of the defective memory cell can be set to the address data of a spare memory cell. In this way, if a data memory has one or more defective memory cells, it can still be used by replacing such defective memory cells with spare memory cells.
One way in which spare memory cells can replace defective memory cells is through a programmable circuit that can include fusible links or the like. A laser may open selected fusible links to thereby redirect a defective memory cell address to a spare memory cell. In other words, a laser can “set” address data for a defective memory cell.
As noted above, a data memory in die form is typically packaged. One of the many types of packages is an epoxy resin package. Once placed in an epoxy resin package, it is usually no longer possible to observe the programmed redundancy information.
While data memories can be tested prior to packaging, sometimes data memories may fail after packaging. Such failures can be the result of defects that take longer to fail or may be caused by defective operation. Because packaging can completely cover a semiconductor memory die, it can be difficult to determine if an address has been set for a defective memory cell. Thus, if a failure occurs in a semiconductor memory after packaging, one cannot determine if the failure has occurred in a previously normal memory cell, in a spare memory cell that has replaced a defective memory cell, or in the redundancy circuit, including fusible links, if present.
One way to determine if an access is to a normal memory cell or a spare memory is to utilize a “roll call” circuit. One particular type of roll call circuit can provide a predetermined output when an address results in the activation of a redundancy circuit (such as one that may include fusible links). A predetermined roll call output can be provided externally to the data memory package. Thus, it can be possible to determine if a data memory access is to a normal memory cell or a spare memory cell.
A first example of a conventional data memory will now be described in conjunction with
FIGS. 5 and 6
.
FIG. 5
is a schematic top view illustrating the internal layout of a data memory in the form of a memory “chip”.
FIG. 6
is a block diagram of a conventional redundancy circuit and result output circuit.
Referring now to
FIG. 5
a memory chip is designated by the general reference character
500
, and is shown to include memory circuits
502
. In the particular example of
FIG. 5
, there are four memory circuits
502
formed in a body substrate
504
. The memory circuits
502
and body substrate
504
can have a rectangular shape. The four memory circuits
502
are arranged into two rows and two columns.
Memory circuits
502
can include a number of normal memory cells, at least one spare memory cell, and a row/column decoder (all not illustrated). Normal memory cells may be accessed according to predetermined address data. A spare memory cell is normally not used. A row/column decoder can decode address data to select a particular memory cell or cells.
The memory chip
500
may also include a number of external connection terminals connected to address input circuits (not illustrated). Address data can be applied to the memory chip
500
by way of such external connection terminals.
When address data is input to the memory chip
500
, such address data can be decoded by row/column decoders and one or more normal memory cells can be accessed. In the case of a write operation, write data on external connection terminals can be written into the accessed normal memory cells. In the case of a read operation, read data can be provided on external connection terminals.
In a “normal” access, address data can access normal memory cells in the memory circuits
502
. However, the memory chip
500
can be set so that particular address data accesses one or more spare memory cells. In particular, prior to any testing, no spare memory cells can be accessed by an address. However, if the memory chip is inspected and a defective normal memory cell is detected, the memory chip
500
can be set so that the address of the defective normal memory cell accesses a spare memory cell.
In the example of
FIG. 5
, the memory chip
500
is shown to further include six redundancy circuits
506
-
a
to
506
-
f
situated between the memory circuits
502
. Redundancy circuits
506
-
a
to
506
-
d
can be row redundancy circuits. One row redundancy circuit (
506
-
a
to
506
-
d
) can be connected to each memory circuit
502
. Redundancy circuits
506
-
e
to
506
-
f
can be column redundancy circuits. One column redundancy circuit (
506
-
e
to
506
-
f
) can be connected to two memory circuits
502
.
Redundancy circuits (
506
-
a
to
506
-
f
) can include fuse include fusible links and an address comparison circuit, or the like. A fuse circuit can thus provide address changing functions and signal generating functions. A fuse circuit may particularly include a fuse ROM. Address data within the fuse ROM may be set by laser cutting to the address of a defective normal memory cell.
An address comparison circuit can compare address data received by external connection terminals. When the received address data corresponds to an address programmed into a fuse ROM, the access destination is changed from a normal memory cell to a spare memory cell. In addition, an address comparison circuit can further output a redundancy signal that indicates a spare memory cell access has taken place. Such a redundancy signal may be provided on one or more external connection terminals as a roll call signal.
A memory chip
500
can also include a result decision circuit
508
and result output circuit
510
. The result decision circuit
508
and result output circuit
510
can include logic OR gates. The result decision circuit
508
is situated centrally with respect to the memory circuits
502
and redundancy circuits (
506
-
a
to
506
-
f
) to minimize connection wiring
512
to the redundancy circuits (
506
-
a
to
506
-
f
).
FIG. 6
shows how six redundancy circuits (
506
-
a
to
506
-
f
) can be connected to a result decision circuit
508
and result output circuit
510
.
In the examples of
FIGS. 5 and 6
, six redundancy circuits (
506
-
a
to
506
-
f
) can be connected to one result decision circuit
508
by six signal wirings
512
. The result decision circuit
508
can be connected to result output circuit
510
by signal wiring
514
.
When defect analysis is performed on a packaged memory chip
500
an address can be applied to access a memory cell. The result decision circuit
508
can determine if the access is to a normal memory cell or a spare memory cell. This determination can be provided to the result output circuit
510
. The result output circuit
510
can provide the determination on one or more external connection terminals. Such a determination can be a

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