Data managing method for memory apparatus

Details Data managing method for memory apparatus Data managing method for memory apparatus

2007-10-09

2007-10-09

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S154000, C711S202000, C365S189011

Reexamination Certificate

active

11115712

ABSTRACT:
A block correlation table includes block addresses of unusable block portions in an irreversibly writeable memory and includes addresses of associated substitute block portions in the irreversibly writeable memory. A request for data stored at a logical address is received from a host processor. A physical address in the irreversibly writeable memory is calculated from the logical address using a fixed mathematical relation. The physical address is compared with the block addresses in the block correlation table. When the physical address does not match any of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the physical address, and when the physical address matches one of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the address of its associated substitute block portion. The read data is transmitted to the host processor.

REFERENCES:
patent: 5226168 (1993-07-01), Kobayashi et al.
patent: 5644539 (1997-07-01), Yamagami et al.
patent: 5749084 (1998-05-01), Huck et al.
patent: 5930825 (1999-07-01), Nakashima et al.
patent: 5946714 (1999-08-01), Miyauchi et al.
patent: 5963738 (1999-10-01), Yamaki et al.
patent: 5968187 (1999-10-01), Robinson
patent: 5991517 (1999-11-01), Harari et al.
patent: 6031758 (2000-02-01), Katayama et al.
patent: 6282645 (2001-08-01), Yamaki
patent: 6341085 (2002-01-01), Yamagami et al.
patent: 6446177 (2002-09-01), Tanaka et al.
patent: 6591329 (2003-07-01), Kakinuma et al.
patent: 6675276 (2004-01-01), Schulze et al.
patent: 2002/0085416 (2002-07-01), Yamagami et al.
patent: 2003/0210587 (2003-11-01), Yamagami et al.
patent: 1209568 (2002-05-01), None
patent: 3-97050 (1991-04-01), None
patent: 3-156524 (1991-07-01), None
patent: 4-133149 (1992-05-01), None
patent: 2000-11677 (2000-01-01), None
patent: 2000-285001 (2000-10-01), None
patent: WO-97/32253 (1997-09-01), None
patent: WO-9844420 (1998-10-01), None
patent: WO-9932977 (1999-07-01), None
patent: WO-00/50997 (2000-08-01), None

Affiliated with

Also associated with

Rating

Data managing method for memory apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data managing method for memory apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data managing method for memory apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3851232