Data link protecting system

Multiplex communications – Wide area network – Packet switching

Patent

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Details

371 111, 340827, H04J 116

Patent

active

053134567

ABSTRACT:
A line interface circuit on the receiving side detects communication failure in terms of an error rate and informs the supervisory and control unit on the receiving side of the occurrence of the failure. The supervisory and control unit on the receiving side in turn switches the line data communications from the receiving side to the transmitting side to another line unused for data communications to inform the supervisory and control unit on the transmitting side of the occurrence of the failure. The supervisory and control unit on the transmitting side switches the line for data communications from the transmitting side to the receiving side to the other line. The switching circuit on the receiving side comprises buffers each inserted in a line and a buffer connected to the common outputs of the buffers so that the supervisory and control unit on the receiving side automatically receives a transmit signal transmitted over a line switched on the transmitting side.

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patent: 5014264 (1991-05-01), Nagler et al.
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patent: 5109296 (1992-04-01), Fukushima et al.

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