Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2007-08-07
2007-08-07
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C327S018000
Reexamination Certificate
active
10520049
ABSTRACT:
According to the IEEE1394 bus protocol, priority is given to isochronous data packets. Data transfer is done in transfer cycles under the control of a cycle master. It depends on the allocated bandwidth for isochronous data how much transport capacity is available in a transfer cycle. To managed the mixed data transfer in one cycle it is specified that the bus nodes not having isochronous data to transfer need to wait with their transmission requests until the end of the isochronous data transfers in the cycle indicated with a sub-action gap. The invention aims to improve the efficiency of data transport for the case that none of the bus nodes need to transfer isochronous data. The data link layer devices according to the invention includes means for checking whether isochronous data is to be transferred and if not they switch over to a no cycle master state, in which the local cycle synchronization events are ignored. The nodes need not wait for a sub-action gap after a local cycle event before drawing asynchronous transmission requests.
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R. Brand: “Iso-Ethernet: Bridging the Gap from WAN to LAN” Data Communications, McGraw-Hill, New York, US, vol. 24, No. 9, Jul. 1, 1985, pp. 103-104,106,108.
M. Tenner: “A bus on a diet-the serial bus alternative-an introduction to the P1394 High Performance Serial Bus”, Intellectual Leverage. San Francisco, Feb. 24-28, 1992, Proceedings of the Computer Society of International Conf., vol. CONF 37, Feb. 24, 1992, pp. 316-321.
The Search Report Date Sep. 29, 2003.
Gaedke Klaus
Heighway Timothy
Schweidler Siegfried
Ferguson Catherine A.
Knoll Clifford
Laks Joseph J.
Levy Robert B.
Perveen Rehana
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