Data length control of access to a data bus

Details Data length control of access to a data bus Data length control of access to a data bus

2000-04-18

2003-10-21

Vo, Tim (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S240000

Reexamination Certificate

active

06636913

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the transfer of both read and write data across a data bus, and, more particularly, to the transfer of data streams in an environment of a plurality of agents attached to the data bus.
BACKGROUND OF THE INVENTION
High capacity bus systems provide the capability of transferring multibyte data streams between host processors and devices attached to the bus system. As one example, the Peripheral Component Interconnect (PCI) bus system is a high-performance expansion bus architecture which offers a low latency path employing PCI bridges through which a host processor may directly access PCI devices. In a multiple host environment, a PCI bus system may include such functions as data buffering and PCI central functions such as arbitration over usage of the bus system.
The incorporated '610 application describes an example of a complex PCI bus system for providing a connection path between a secondary PCI bus, to which are attached a plurality of agents, such as channel adapters, and at least one primary bus to which is attached a peripheral device server. The incorporated '610 application additionally defines many of the terms employed herein, and such definitions are also available from publications provided by the PCI Special Interest Group, and will not be repeated here. Complex PCI bus systems, such as that of the incorporated '610 application, employ arbitration between commands from the attached channel adapters on the bus to manage the usage of the bus system in an efficient manner.
Computer data storage systems may employ high capacity bus systems to provide fast data storage and retrieval between host processors, such as network servers, via channel adapters and the bus system, to attached storage servers having storage devices, cache storage, and/or non-volatile cache storage. It is advantageous to provide data storage and retrieval that operates at relatively fast speeds which approach or match the speeds of the host processors, or that release the host processors, such that the host processors are not slowed. Typically, the host systems coupled to the channel adapters attempt to write and to read large amounts of data at once in the form of multibyte data streams. The bus architecture, such as for a PCI bus system, does not define the total amount of data to be accessed in an operation, and balances the need for high throughput for a given channel adapter with the need for low latency between accesses by agents by requiring that the write and read operations be broken up. To allow a single channel adapter to monopolize the bus to complete the total data transfer in a single transaction would be very inefficient with regard to the bus system as a whole, and would substantially reduce the effective bandwidth of the bus system.
Hence, the bus architecture, e.g., of the PCI bus system of the incorporated '610 application, may attempt to limit single data transfers to major blocks of data made up of small blocks or groups of data, such as 512 bytes. Upon the transfer of a small block of data, the bus arbiter will grant access to the bus to another channel adapter, for example, in a round-robin fashion. The next channel adapter may then transfer a small block of data, etc., and the process will subsequently cycle back to the original channel adapter, which may then transfer another small block of data. Thus, all of the channel adapters having requests to transfer data will be satisfied, reducing the latency of the bus system.
In conducting write operations, channel adapters in a PCI bus system, under PCI protocol, are required to have latency timers which force the channel adapter to give up the bus after a predetermined time. Thus, the channel adapters will have their grants deasserted immediately when beginning the write, and the latency timers will determine when they give up the PCI bus. The channel adapter latency timers are set to not exceed 512 byte transfers so as not to overrun write data buffers, for example, in the PCI bus adapter. However, tuning the latency timers of the channel adapters to move exactly 512 bytes of data each time is difficult if not impossible. As the result, channel adapters that are performing a single write data transfer of 512 bytes or multiple 512 byte transfers have to arbitrate for the PCI bus more than they would normally have to if they were able to transfer 512 bytes each time that they had access to the PCI bus. This behavior degrades the performance of the channel adapter, the PCI bus, and the bus system.
In conducting read operations, the channel adapters may request to read, for example, a large block of 4 K bytes, which is supplied as a number of small block 512 byte reads under the control of the PCI bus manager. The PCI bus system will deassert the grant from the requesting channel adapter while the bus system is prefetching and gathering the requested data, and will issue the grant after the first 512 bytes of the data has been gathered, for example, in a FIFO buffer, as discussed in the incorporated '610 application. Once the first 512 bytes of data is ready to be presented to the channel adapter, the adapter's request will be granted upon the round-robin arbitration, and the transfer of the data begun. The remainder of the requested data will, in the mean time, be prefetched in 512 byte increments. If the channel adapter is faster reading the 512 bytes of gathered data than the PCI bus system is in gathering the next 512 bytes, the PCI bus system will deassert the grant because there is no more available data. The channel adapter will have its “frame” and “initiator ready” signals asserted because it wants 4 K bytes of data. Even though its grant has been deasserted, the channel adapter must wait for the PCI bus adapter to assert a “stop” signal before it can deassert the “frame” and “initiator ready” signals to indicate the last data phase, and thereby release the PCI bus. Specifically, the PCI bus adapter has a PCI retry counter which counts clocks while the adapter looks for “initiator ready” and “target ready” signals to indicate a transfer of data. The counter is intended to hold the bus available so that the PCI bus adapter may have time to transfer the data, forcing a retry if the counter expires. Thus, the “stop” signal will not be asserted until the PCI retry counter has expired. This retry count is set to a predefined time period, such as 1.5 microseconds. The PCI bus is thus in use but not transferring data for the 1.5 microseconds, degrading bus performance.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a more precise control over access to the bus system, and thereby increase the performance of the bus system.
Disclosed are a method and system for controlling access to a bus for transferring data in the form of multibyte data streams. Data transfer agents are coupled to and request access to the bus to transfer data thereon. The system for controlling access to the bus comprises a bus arbiter coupled to the bus and responsive to the access requests of the data transfer agents, granting access to the bus to one data transfer agent for transferring data. A data length counter accumulates, during the grant of access, signals indicating the length of the data transferred between the bus and the data transfer agent. The data length counter indicates completion of a predetermined length of transferred data, and bus arbiter logic coupled to the data length counter and the bus arbiter, responds to the data length counter indicating the transfer completion, causing the bus arbiter to terminate the grant of access to the data transfer agent.
The data length counter may comprise a data length register storing a value indicating the predetermined length of transferred data, and a comparator comparing the accumulated length of the transferred data to the predetermined length value stored in the data length register. The data length counter, upon the comparator indicating the accumulated length equals the predetermined

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