Data latching circuit for read-out operations of data from memor

Details Data latching circuit for read-out operations of data from memor Data latching circuit for read-out operations of data from memor

1997-05-27

1998-11-24

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Differential sensing

365194, 36518905, 3651852, G11C 700

Patent

active

058417192

ABSTRACT:
Dummy memory cells are provided which have substantially the same structure as the main memory cells. A main sense amplifier is provided for reading out data from the main memory cells. A dummy sense amplifier is provided for reading out data from the dummy memory cells. A data latching circuit is provided for latching the data outputted from the main sense amplifier. Read out operations from the dummy memory cells are made at the same time as the read out operations from the main memory cells. The data latch circuit latches data outputted from the main sense amplifier by utilizing the timing when the dummy sense amplifier outputs data of the dummy memory cells.

REFERENCES:
patent: 5029135 (1991-07-01), Okubo
patent: 5325337 (1994-06-01), Buttar
patent: 5671180 (1997-09-01), Higuchi
patent: 5694369 (1997-12-01), Abe

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