Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
1999-06-24
2002-03-12
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
Reexamination Certificate
active
06357015
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a data interface for communicating data between processors and a high-speed-communication system using the interface.
BACKGROUND ART
The present invention relates to an interface which is capable of, at high speed, communicating (transmitting and receiving) data between microprocessors when, for example, a mechanical structure, e.g., an electric motor, which must be controlled, is controlled by a processing system having a multiprocessor structure with a plurality of microprocessors, and to a high-speed-communication system using the interface.
Hitherto, when control is performed by a plurality of microprocessors, a method using serial transmission or parallel transmission or transmission using a dual port memory has been employed, in which commands, messages and various control information items are communicated between a microprocessor (hereinafter called a “control-side processor”) for receiving from an object to be controlled information indicating the state of the object, performing a calculation from the received control information, and directly issuing a command to the object to be controlled and a microprocessor (hereinafter called a “central processor”) for issuing a command to a sole processor or a plurality of control-side processors in accordance with information obtained from a transmission interface, man-machine interface or an external interface. The transmission using the dual port memory is performed in such a manner that read/write from the control side, the central side or both sides to and from the dual port memory is performed in accordance with a transfer procedure previously determined between the control side and the central side to communicate commands, messages and various control information items.
When various control information items are communicated among one central processor and a plurality of control-side processors, the following conditions must be satisfied:
(1) Although the timing at which information is transmitted from the central processor to each of the control-side processor is relatively long compared to the short time high-speed operation cycle of the high-speed sampling performed in each of the control-side processors, data communication must be reliably performed during the transmission timing;
(2) Since the data which must be communicated between the central processor and each of the control-side processors can have tens to hundreds of word units, the circuit function must be larger than the volume of data which can be transmitted in one transmission operation;
(3) Considering the short-time high-speed operation cycle of high-speed sampling performed by each of the control-side processors, the central processor is inhibited from performing a process which affects the operation time of each of the control-side processors and which is longer than the operation period (cycle) for each of the control-side processors. Also, when the central processor transmits information to and receives information from each of the control-side processors, the central processor must not perform a process which affects its processing time and which is longer than its operation cycle;
(4) Since control information data which is communicated between the central processor and the control-side processor in a single operation is in the form of a block having conformability or unity, an occurrence in which a success in communication of certain data items and a failure in communication of certain data items in the same block must be inhibited.
To satisfy the above-mentioned conditions, a method of realizing a operation architecture and a circuit between the single central processor and a plurality of control-side processors has been as follows.
In conventional serial transmission, synchronous or asynchronous transfer can be selected. If one word has a volume of one byte and information about one word is communicated, two processors attempting to communicate are able to conduct the communication without mutual interference. However, if the quantity of data, which must be communicated, is larger than the above-mentioned quantity, the receiver side must inform the transmission-side processor of receipt of data to permit the transmission-side processor to transfer next data. As a result, two processors having different operation cycles must perform a handshake operation to send the confirmation information “completion of transmission/incompletion of transmission” and “completion of receipt/incompletion of receipt” between the central processor and the control-side processor which have communicated with each other. To perform the process for confirming communication completion of control information data, both transmission and receipt-side processors undesirably interfere in the other's operation processing periods with each other. Thus, the processing time is excessively elongated.
It might be considered feasible to arrange the conventional serial transmission in such a manner that a large buffer for storing data in a quantity of tens to hundreds of words is provided as a received-data storage buffer of an interface circuit block so that a receipt completion flag is set when a predetermined number of data has been received to enable the receiving-side processor to determine whether start of the data receiving operation is permitted. Even so, since the timing at which the control-side processor or the central processor reads data from the buffer of the serial interface and the timing at which the serial interface supplies data to the buffer coincide with each other, there is the great possibility that the processor with a longer operation period fails to receive data. Thus, data cannot be reliably received with predetermined sampling and the reliability in receiving data deteriorates.
To prevent this, a dedicated high-speed-communication processor must be provided for each of the two communication terminals to exclusively perform error processing and the like. In this case, a communication processor is employed, resulting in that a problem arises which is the same as that experienced with the communication between the central processor and the control-side processor to determine a procedure for transferring data of control information between the communication processor and the central processor or the control-side processor without affecting the mutual operation processes of the processors.
The parallel transmission must be performed in such a manner that control information data is communicated at a transfer timing synchronous between the two sides. If either side performs another process during the process for communicating control information data attributable to interruption or the like, data transfer cannot be performed. In this case, either of the two sides always performs the interruption process for another and thus the mutual operation processing periods (cycles) are allowed to interfere with each other, thus causing the processing time to be excessively elongated.
In a transmission using a dual port memory, access can be inhibited by a BUSY terminal or the like to inhibit access for either side when the other side is making an access. Thus, the two sides are able to individually perform operations without the necessity of establishing synchronization. However, a central processor having a long operation processing period fails to write control information data on the dual port memory (that is, transmit data) when each of the control-side processors with short operation processing periods are reading data in the dual port memory in advance. Although data can again be transmitted after the failure, in the communication of the control information with keeping a conformability or unity of the sequential data items which are transmitted in one transmission operation, it is not possible to provide the control-side processor with the time inhibiting reading of the dual port memory, by means of the circuit structure of only the dual port memory. Moreover, the operation for again transmitting data from the
Gokan Hiroshi
Ohtsuji Akio
Yamakawa Shigeki
LandOfFree
Data interface and high-speed communication system using the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data interface and high-speed communication system using the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data interface and high-speed communication system using the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2855966