Data input/output circuit for semiconductor memory device

Details Data input/output circuit for semiconductor memory device Data input/output circuit for semiconductor memory device

1999-08-18

2002-09-24

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

For complementary information

Reexamination Certificate

active

06456543

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data input/output circuit for a semiconductor memory device, and in particular to an improved data input/output circuit which is capable of enhancing an operation performance of a latch-type sense amplifier by minimizing a load of a data line.
2. Description of the Background Art
FIG. 1
is a schematic block diagram illustrating a conventional data input/output circuit for a semiconductor memory device.
As shown in
FIG. 1
, the data input/output circuit for a conventional semiconductor memory includes a memory cell array
1
for storing cell data, a latch-type sense amplifier
2
connected with the memory cell array
1
via the data lines DL and /DL for amplifying a data outputted from a the memory and outputting the amplified data to the output buffer(not shown), and a write driver
3
for writing an external data into the memory cell array
1
, and is connected with the data lines DL and /DL.
FIG. 2
is a schematic circuit diagram illustrating the latch-type sense amplifier
2
in the circuit of FIG.
1
. As shown in
FIG. 2
, the latch-type sense amplifier
2
includes a PMOS transistor PM
1
having its channel connected between a power supply voltage VDD and a node
52
and receiving a sense amplifier enable signal SE through the gate thereof, a first and second CMOS inverters
30
and
31
connected in parallel between nodes
52
and
53
and a NMOS transistor NM
1
having its channel connected between a node
53
and a ground voltage VSS and receiving an inverted sense amplifier enable signal /SE through the gate thereof.
The first CMOS inverter
30
includes a PMOS transistor PM
2
and a NMOS transistor NM
2
having their channels connected in series between nodes
52
and
53
, and having the gates commonly connected with the data line /DL via a second input/output node
51
of the second CMOS inverter
31
. Also, the second CMOS inverter
31
includes a PMOS transistor PM
3
and a NMOS transistor NM
3
having their channels connected in series between nodes
52
and
53
, and having the gates commonly connected with the data line DL via a first input/output node
50
of the first CMOS inverter
30
.
The operation of the conventional data input/output circuit of the semiconductor memory device will be explained.
In the read mode, cell data is outputted from the memory cell array
1
based on address signals (a column address signal and a row address signal) and loaded onto the data lines DL and /DL. When the cell data is sufficiently transmitted to the latch-type sense amplifier
2
via the data lines DL and /DL, the sense amplifier enabled signals SE and /SE are enable, so that the latch-type sense amplifier
2
is operated. Assuming that the cell data read from the memory cell array
1
are D and /D, respectively, the cell data D of a high level and the cell data /D of a low level are inputted to the second CMOS inverter
31
via the first input/output node
50
and the first CMOS inverter
30
via the second input/output node
51
, respectively. Thus, the PMOS transistor PM
2
of the first CMOS inverter
30
and the NMOS transistor NM
3
of the second CMOS inverter
31
based on the cell data /D and D, respectively, are turned on. Therefore, the cell data D and /D are amplified and latched at the first and second input/output node
50
and
51
, thereby outputting to the output buffer(not shown).
In the write mode, a write driver
3
, which maintains a high impedance state in the read mode, transmits cell data over to the data lines DL and /DL, a certain cell in the memory cell array
1
is selected based on address signals (a column address signal and a row address signal). Therefore, the cell data loaded in the data lines DL and /DL are stored into the selected cell of the memory cell array
1
.
However, an input node and an output node, that is, the identical input/output nodes
50
and
51
, of the latch-type sense amplifier
2
are commonly connected. Also, the first and second input/output nodes
50
and
51
of the latch-type sense amplifier
2
are connected with the data lines DL and /DL having a long path, respectively. Thus, the loading of the data lines DL and /DL at the input node, which is generated due to the data line having a long path, is identically reflected at the output node, thereby decreasing the speed at which the data is amplified. In addition, when a size of the latch-type sense amplifier is designed to be large to minimize the above problems, the area of the entire chip and the current consumption are undesirably increased.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a data input/output circuit for a semiconductor memory device which overcomes the aforementioned problems encountered in the background art.
Also the present invention provides a data input/output circuit for a semiconductor memory device which is capable of enhancing the operation performance of the sense amplifier by minimizing the load of the data line in the read mode.
A data input/output circuit for a semiconductor memory includes a memory cell array, a latch-type sense amplifier for amplifying the cell data transmitted from the memory cell array in a read mode, a switching transistor for controlling a transmission of the cell data, connected between the memory cell array and the latch-type sense amplifier, and a write driver for storing an externally inputted cell data into the memory cell array in a write mode. The transmission gate is turned on at an initial state of the read operation mode in accordance with a read enable signal, and is turned off when the latch-type sense amplifier is operated in accordance with a sense amplifier enable signal. The switching transistor separates the data line loading from the latch-type sense amplifier at the operation point of the latch-type sense amplifier, so that the operation speed of the sense amplifier is enhanced.
Additional advantages, and features of the invention will become more apparent from the description which follows.


REFERENCES:
patent: 4905317 (1990-02-01), Suzuki et al.
patent: 5539691 (1996-07-01), Kozaru et al.
patent: 5684750 (1997-11-01), Kondoh et al.
patent: 5724292 (1998-03-01), Wada
patent: 5982690 (1999-11-01), Austin
patent: 6052328 (2000-04-01), Ternullo, Jr. et al.

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