Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2003-01-13
2004-05-11
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06734707
DESCRIPTION:
FIG. 2 is a circuit diagram of a data input circuit 200 according to an exemplary embodiment of the present invention. Referring to FIG. 2 , the data input circuit 200 includes N latching units 210 _i and a bus 250 , where i is an integer from 1 to N, and N is a natural number greater than 2. For convenience, the N latching units 210 _i will now be described as first through N th latching units 210 _i.
Each of the first through N th latching units 210 _ 1 through 210 _N latches one of N groups of data D<0> through D<N−1> in response to a reference clock SC. In particular, the first latching unit 210 — 1 latches the first group of data D<0>, the second latching unit 210 _ 2 latches the second group of data D<1>, and the remaining latching units 210 _i latch corresponding groups of data, respectively (i is an integer from 3 to N). The reference clock SC may be a signal input via a clock pin (not shown) of a semiconductor device, and may be used as a fetch signal when fetching N groups of data. In an exemplary embodiment, one group of data includes one bit. Thus, the N groups of data D<0> through D<N−1> include N bits.
The bus 250 transmits the reference clock SC and data D<j> input via outer pins of a semiconductor device, and data D<j> to the first through N th latching units 210 _i, respectively, where j is an integer from 0 to N_ 1 and i is an integer from 1 to N.
In an exemplary detailed configuration of the first through N th latching units 210 _i, each of these latching units 210 _i may include a clock buffer 23 i , a data buffer 24 i , N−1 dummy elements Cd and a latch 220 _i.
The clock buffers 23 i buffer the reference clock SC, and the data buffers 24 i buffer a corresponding group of data out of N groups of data D<j> (i is an integer from 1 through N and j is an integer 0 through N−1). That is, the data buffer 241 of the first latching unit 210 _ 1 buffers the first group of data D<0>, and the data buffer 242 of the second latching unit 210 _ 2 buffers the second group of data D<1>. Also, the buffers 24 i of the other latches 210 _i buffer corresponding groups of the data, respectively (i is an integer from 3 to N).
Each dummy element Cd receives the N groups of data, except for a group of data input to the data buffer 24 i of a latching unit 210 _i to which the dummy element Cd belongs. For example, the N−1 dummy elements Cd of the first latching unit 210 _ 1 receive the second through N th groups of data D<j>, respectively (j is an integer from 1 to N−1). The N−1 dummy elements Cd of the second latching unit 210 _ 2 receive the first group of data D<0> and the third through N th groups of data D<j>, respectively (j is an integer from 2 to N−1). Similarly, the dummy elements Cd of the third through N th latching units 210 _i receive corresponding groups of data, respectively (i is an integer from 3 to N).
In an exemplary embodiment, each dummy element Cd is a capacitor having the same or substantially the same capacitance as the clock buffer 23 i (i is an integer from 1 to N).
The latch 220 _i latches data output from the data buffer 24 i in synchronization with a signal output from the clock buffer 23 i (i is an integer from 1 to N). That is, the latch 220 _ 1 of the first latching unit 210 _ 1 latches the first group of data D<0>, and the latch 220 _ 2 of the second latching unit 210 _ 2 latches the second group of data D<1>. Likewise, the latches 220 _i of the other latching units 210 _i latch corresponding groups of data, respectively (i is an integer from 3 to N) as in the data buffers 241 and 242 of the first and second latching units 210 _ 1 and 210 _ 2 .
It is assumed that the clock buffer 23 i and the data buffer 24 i have the same or substantially the same size and/or structure (i is an integer from 1 through N), and each clock buffer 23 i and each data buffer 24 i have the same or substantially the same capacitance. Also, the value of the capacitance o
REFERENCES:
patent: 5489901 (1996-02-01), Fukuda et al.
patent: 5715198 (1998-02-01), Braceras et al.
patent: 6169435 (2001-01-01), Fujii et al.
patent: 56125132 (1981-10-01), None
patent: 409311742 (1997-12-01), None
Jang Su-bong
Kim Kyu-hyoun
Song Ho-young
Harness Dickey
Le Dinh T.
Samsung Electronics Co,. Ltd.
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