Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement
Reexamination Certificate
2007-02-20
2007-02-20
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Input noise margin enhancement
C326S022000, C326S021000, C326S090000, C326S086000, C326S115000
Reexamination Certificate
active
11027631
ABSTRACT:
A data input buffer for use in a semiconductor device, including: a detection unit for receiving a reference voltage signal and an input data signal through a first input terminal and a second input terminal respectively in order to detect a voltage level of the input data signal based on a result of comparing the input data signal with the reference voltage in response to a clock enable signal inputted through a third input terminal; and a noise elimination unit connected between the first input terminal and the third input terminal for eliminating a noise of the reference voltage signal.
REFERENCES:
patent: 6288590 (2001-09-01), Sandhu
patent: 6366113 (2002-04-01), Song
patent: 6768691 (2004-07-01), Kumazaki et al.
patent: 6768697 (2004-07-01), Labrum et al.
patent: 2003/0223303 (2003-12-01), Lamb et al.
patent: 2004/0066683 (2004-04-01), Hartmann et al.
Ahn Jin-Hong
Kang Hee-Bok
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Tran Anh Q.
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