Data input buffer circuit for use in a semiconductor memory devi

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 3072968, 307451, H03K 190175, H03K 190948

Patent

active

053550331

ABSTRACT:
The invention is to provide a data input buffer which can attain stably an input trip level regardless of a variation of power source voltage, for use in a semiconductor memory device, and particularly to provide a data input buffer which is not affected by a variation of power source voltage. The data input buffer circuit comprises a conductive passage, coupled between the power source voltage and a level sensing node, for adjusting the amount of an current according to a level of input voltage; and an insulation gate field effect transistor, with one end of channel of the transistor connected to the conductive passage, other end of channel of the transistor connected to ground voltage terminal and a gate of the transistor to which voltage is applied according to a level of the power source voltage.

REFERENCES:
patent: 4464587 (1984-08-01), Suzuki et al.
patent: 4687954 (1987-08-01), Yasuda et al.
patent: 4833342 (1989-05-01), Kiryu et al.
patent: 4929853 (1990-05-01), Kim et al.
patent: 5034623 (1991-07-01), McAdams

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