Data input buffer circuit

Details Data input buffer circuit Data input buffer circuit

1999-12-02

2001-06-05

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

C326S082000, C365S233500, C365S189050

Reexamination Certificate

active

06242940

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data input buffer circuit, and in particular to a data input buffer circuit which is capable of decreasing a current consumption caused when a data signal is transited in a write disable interval by maintaining a state that a data signal is transited in a write enable interval in the write enable interval and accurately reading and writing data by obtaining a substantial data holding time(tDH) margin.
2. Description of the Background Art
FIG. 1
illustrates a conventional input buffer circuit which includes a first basic input data buffer circuit
11
which includes a first NOR-gate NOR
1
for NORing a data control signal WECS formed by mixing a write enable signal WE and a chip selection signal CS and a first data signal DIN
1
inputted into an external first data pad, a first inverter INV
1
for inverting an output of the first NOR-gate NOR
1
, a first delay unit DE
1
for delaying an output of the first inverter INV
1
for a certain time Td
1
and outputting a first input data signal DATAIN
1
, and a first data transition detection unit
20
for detecting a transition of the first data control signal DINT
1
from the first inverter INV
1
and outputting a first data transition detection signal DTD
1
. There are further provided data transition detection units
21
~
1
n
for receiving second~n-h data signals DIN
2
~DINn, and a data transition detection signal mixing unit
30
for mixing first~n-th data transition detection signals DTD
1
~DTDn outputted from the data transition detection units
2
~
2
n
of the first~n-h basic data input buffer circuits
11
~
1
n
which are configured in a similar method compared to the first basic input data buffer circuit
11
.
The number of basic data input buffer circuits is determined depending on the number of input/output pins.
FIG. 2
illustrates a first data transition detection unit
21
. As shown therein, there are provided a second inverter INV
2
for inverting a first data control signal DINT
1
from the first inverter INV
1
, a second delay unit DE
2
for delaying an output of the second inverter INV
2
for a certain time, a third inverter INV
3
for inverting an output of the second delay unit DE
2
, first and second transmission gates TG
1
and TG
2
controlled by an output of the second delay unit DE
2
and an inverted signal thereof for selectively transmitting a first data control signal DINT
2
from the first inverter INV
1
and an inverted signal thereof, a fourth inverter INV
4
for inverting an output from the first or second transmission gates TG
1
or TG
2
, and a first NMOS transistor NM
1
for receiving an output of the fourth inverter INV
4
via its gate and outputting a first data transition detection signal DTD
1
via its drain. In addition, the construction of a data transition detection unit(not shown) of the second through n-th basic data input buffer circuits
12
~
1
n
is constructed in the same manner as the first data transition detection unit
21
.
FIG. 3
is a circuit diagram illustrating a detection signal summing unit
30
for summing the first through n-th data transition detection signals DTD
1
~DTDn. As shown therein, there are provided a first PMOS transistor PM
1
and a second NMOS transistor NM
2
connected in series between a power voltage VCC and a ground voltage VSS and having their commonly connected drains which receive first through n-th detection signals DTD
1
~DTDn, second through fourth PMOS transistors PM
2
~PM
4
connected parallely with the first PMOS transistor PM
1
, a fifth inverter INV
5
for inverting a chip selection signal CS and applying the inverted signal to the second NMOS transistor NM
2
and the third PMOS transistor PM
3
, respectively, a sixth inverter INV
6
for inverting the voltages of the commonly connected drains of the fourth PMOS transistor PM
3
and the second NMOS transistor NM
2
and applying to the gate of the fourth PMOS transistor PM
4
, a seventh inverter INV
7
for inverting an output of the sixth inverter INV
6
, a third delay unit DE
3
for delaying an output of the seventh inverter INV
7
for a certain time, a second NOR-gate NOR
2
for NORing an output of the third delay unit DE
3
and an output of the seventh inverter INV
7
, a first NAND-gate ND
1
for NANDing an output of the second NOR-gate NOR
2
and a chip selection signal CS and outputting to the gates of the first and second PMOS transistors PM
1
and PM
2
, respectively, and an eighth inverter INV
8
for inverting a voltages of the commonly connected drains of the first through fourth PMOS transistors PM
1
~PM
4
and the second NMOS transistor NM
2
and outputting a summing signal DTDSUM of a data transition detection signal.
The operation of the conventional data input buffer circuit will be explained with reference to the accompanying drawings.
First, as shown in
FIGS. 4A and 4B
, the write enable signal WE and the chip selection signal CS are summed for thereby generating a write control signal WECS as shown in FIG.
4
C. This write control signal WECS is summed with the first data signal DIN
1
as shown in
FIG. 4D
inputted into an external first data pad, so that a first data control signal DINT
1
as shown in
FIG. 4E
is generated.
The first data control signal DINT
1
is delayed by the first delay unit DE
1
for a certain time and is outputted as a first input data signal DATAIN
1
as shown in FIG.
4
H.
The first data transition detection unit
21
generates a first data transition detection signal DTD
1
, as shown in
FIG. 4F
, for detecting the transition of the first data control signal DINT
1
.
When the second through n-th data transition detection signals DTD
2
~DTDn are outputted from the second n-th data transition detection units
22
~
2
n
, the data transition detection signal summing unit
30
sums the first through n-th data transition detection signals DTD
1
~DTDn for thereby generating a data transition detection signal summing signal DTDSUM.
The thusly generated data transition detection signal summing signal DTDSUM is used as a control signal when the semiconductor memory apparatus operates in the write mode.
However, the data control signal is disabled when the write control signal WECS is enabled and even disabled(transited from low to high), so that a current flow path is formed at an unnecessary interval for thereby increasing the current consumption. A data control signal is delated for obtaining a data hold time dDH margin using the first delay unit DE
1
. In this case, a certain variation may be produced due to various processes. Therefore, in order to obtain an enough data hold time tDH margin, a lot amount of inverters is used for a process margin of the first delay unit DE
1
because an input data signal is transited at the write disable interval, and an invalid data may be written.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a data input buffer circuit which is capable of decreasing a current flow path due to a transition of an input data signal when a write enable signal WECS is disabled and preventing an invalid data from being written by obtaining an enough data hold time tDH without an increase of a delay device.
To achieve the above objects, there is provided a data input buffer circuit which includes a first basic circuit which includes a first NOR-gate for NORing a first control signal and a first data signal, a first inverter for inverting an output of the first NOR-gate, a first data maintaining unit for maintaining an enabled state of a first data control signal which is an output of the first inverter, and a first data transition detection unit for detecting a transition of the first data control signal and outputting a first data transition detection signal, second through n-th basic circuits constructed similarly with the first basic circuit for receiving second through n-th data signals and outputting second through n-th input data signals, a data transition detection signal summing unit for summing first thro

Affiliated with

Also associated with

Rating

Data input buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data input buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data input buffer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2536674