Data input buffer

Details Data input buffer Data input buffer

1999-06-29

2001-01-09

Nguyen, Viet Q. (Department: 2818)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S062000, C326S063000, C326S080000, C326S081000, C327S100000

Reexamination Certificate

active

06172524

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a data input buffer for buffering external input signals into signals suitable for internal signals in a semiconductor memory device, and more particularly to a data input buffer by which external input signals with two different standards are converted into a CMOS signal by means of a single circuit.
2. Description of the Prior Art
Generally, the data input buffer is commonly classified into two types: a CMOS invertor type and a differential amplifier type having a current mirror structure.
Referring to
FIG. 1
, there is shown a circuit diagram for illustrating a first embodiment of a conventional data input buffer. The circuit includes a CMOS invertor for converting an externally input signal of a Low Voltage Transistor-Transistor Logic (hereinafter called LVTTL) standard into an internal CMOS signal, which is consisted of P and N channel MOS transistors MP
11
and MN
11
connected serially between the external supply power and the ground.
The operation of the data input buffer having the above construction will be now explained below.
In case that the difference between the potential of the externally input signal Vin and the external supply power Vext is lower than the threshold voltage Vt of the P channel MOS transistor MP
11
, the P channel MOS transistor MP
11
will be at a saturation region, while the N channel MOS transistor MN
11
will be at a cut-off region. Thus, the external supply power Vext is transferred to an output terminal VOUT through the P channel MOS transistor MP
11
which is turned on, and thus the output terminal Vout maintains a high level.
However, in case that the difference between the potential of the input signal Vin and the ground voltage Vss is higher than the threshold voltage Vt of the N channel MOS transistor MN
11
, the N channel MOS transistor MN
11
will be at a saturation region, while the P channel MOS transistor MP
11
will be at a cut-off region. Thus, the output terminal VOUT will be grounded through the N channel MOS transistor MN
11
which is turned on, and thus the output terminal Vout maintains a low level.
In other words, if the input signal Vin is High, the output terminal Vout becomes Low and if the input signal Vin is Low, the output terminal Vout becomes High. At this time, the input potential at which the potential of the output terminal Vout changes from Low to High or from High to Low, becomes a trip point of the invertor. In order to increase immunity against the noise of the input signal, the W/L ratio of the P, N channel MOS transistors MP
1
and MN
11
are adjusted to have the trip point positioned at the middle between the minimum value of the high potential Vih and the maximum value of the low potential Vil, which are the LVTTL signal standards.
However, in case of Stub Series Terminated Logic (hereinafter called SSTL) which emerges as a new high-speed signal connection standard, it additionally requires a reference voltage Vref for deciding a High level or a Low level of the signal. In addition, as the variation width of High or Low signals from the reference voltage Vref is not so large, when the invertor-type input buffer shown in
FIG. 1
is used, both the P, N channel MOS transistors MP
11
, MN
11
will exist at an ohmic region. Thus, the inverter-type input buffer has disadvantages that it increases unnecessarily a power consumption and also decreases the degree of signal determination.
Referring now to
FIG. 2
, there is shown a circuit diagram for illustrating a second embodiment of a conventional data input buffer, which particularly shows a construction of a differential amplifier circuit having a current mirror structure which is suitable for the SSTL signal standard.
The data input buffer shown in
FIG. 2
includes two N channel MOS transistors MN
21
, MN
22
, with a gate of the MOS transistor MN
21
being applied with an input signal Vin and a gate of the MOS transistor MN
22
being applied with a reference voltage Vref; two P channel MOS transistors MP
21
, MP
22
respectively connected between the drains of the two N channel MOS transistors MN
21
, MN
22
and the external supply power Vext, each gate of which is commonly connected to the drain of the N channel MOS transistor MN
21
; and an N channel MOS transistor MN
23
connected between the common source connection node of the two N channel MOS transistors MN
21
, MN
22
and the ground Vss, for controlling the operation of the entire circuit using an externally applied bias potential.
The principle of the operation will be below explained in detail by reference to FIG.
2
. If the potential of the input signal Vin is higher than the reference voltage Vref, the potential difference between the gate-source of the N channel MOS transistor MN
21
to which the input signal Vin is applied, becomes higher than that between the gate-source of the N channel MOS transistor MN
22
to which the reference voltage Vref is applied. Thus, a bias voltage Vbias is applied to the N channel MOS transistor MN
23
the channel length of which is longer than that of the N channel MOS transistors MN
21
, MN
22
, thereby making a constant amount of current flow through the transistor MN
23
. As a result, the current supply power of the transistor MN
21
becomes larger than that of the transistor MN
22
.
Accordingly, the drain voltage of the transistor MN
21
becomes lower than that of the transistor MN
22
, and the effective resistance value of the transistors MP
21
, MP
22
is accordingly varied. As the potential difference between the gate-source of the transistor MP
21
connected between the transistor MN
21
and the external supply power Vext becomes further great to increase its effective resistance value, an external high supply power Vext is transmitted to the output Vout via the transistor MP
22
the effective resistance value of which is small relatively. Thus, a High signal is outputted via the output Vout.
On the contrary, if the potential of the input signal Vin is lower than the reference voltage Vref, the transistor MN
22
will be more rapidly turned on, this making the potential of the output Vout flow into the ground Vss. Thus, a Low signal will be outputted via the output Vout.
As a result, the differential amplifier circuit as described above has disadvantages that it makes a constant level of current flow on it, and it must generate internally a bias voltage Vbias to drive the circuit for controlling the signal determination potential Vref and the current flow at a saturation region.
Conventionally, in order to satisfy the LVTTL and SSTL signal standards, a method of selectively on/off the CMOS inverter circuit shown in FIG.
1
and the differential amplifier circuit shown in FIG.,
2
is used. However, even in this case, it has a problem that it is difficult to prevent current from being consumed because a path of an unnecessary current generated from the differential amplifier is established, and that an unselected circuit consumes power because only a selected circuit is used. Also, there is a problem in that chip size increases.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a data input buffer in which a buffering circuit suitable for two different externally input signal standards is formed as a single circuit, even without a static flow of current and generation of an internal bias voltage, so that the two different externally input signals can be converted into CMOS signals being the internal signal standard.
To accomplish the above object, the data input buffer comprises a first switching circuit connected between an external supply power and a node and controlled by a first determination signal, a second switching circuit connected between the node and a ground terminal and controlled by a second determination signal, and a buffering circuit operated as a SSTL buffer or a LVTTL buffer according to operations of the first and second switching circuits.


REFERENCES:
patent: 5300835 (1994-04-01), Assar et al.
patent: 55

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