Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-08-14
2007-08-14
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S154000
Reexamination Certificate
active
10640465
ABSTRACT:
The present invention is directed to a system and method of testing using a data image cache. An image server is coupled to one or more test beds to perform testing and/or debug operations on one or more components. Each test bed has one or more test slots to receive the one or more components. The test bed is preferably a motherboard. The motherboard may be in normal operation or may be placed in sleep mode during testing or debugging.
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Johansen Jonathan A.
Kroening James L.
Mund Keith
Andersen Jeffery M.
Gateway Inc.
Suiter Sean Patrick
Suiter Swantz PC LLO
Thai Tuan V.
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