Data I/O buffer control circuit

Details Data I/O buffer control circuit Data I/O buffer control circuit

1999-09-28

2002-01-15

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S086000, C326S093000

Reexamination Certificate

active

06339343

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a control circuit and more particularly, a data input/output buffer control circuit for a memory device.
2. Background of the Related Art
In general, a DRAM, a combination of integrated devices, is widely used as a memory device with a high packing density. Unfortunately, the DRAM has a long data read time and low operational speed due to delayed command signals such as RASB and CASB, and a read operation based a Y-address signal. Accordingly, a SDRAM has been developed as an alternative to DRAM for faster read and operational speeds. In the SDRAM, data input and data outputs are implemental using a single input/output pad. Further, both the data input buffer and the data (output buffer are connected to the data input/output pad.
FIG. 1
illustrates a related art circuit for controlling data input/output buffers for the SDRAM. The data input/output buffers include an input/output (I/O) pad
1
for data input or output, the data input buffer
2
, the data output buffer
5
, and the data output buffer control unit
10
. The data input buffer
2
has a first PMOS transistor
3
and a first NMOS transistor
4
for input of data to the SDRAM through the I/O pad
1
, and the data output buffer
5
has a NAND gate
6
, a NOR gate
7
, a PMOS transistor
8
, and a NMOS transistor
9
, for providing data from the SDRAM to the I/O pad
1
. The data output buffer control unit
10
generates a control signal DOEB in response to a clock signal CLK and a read command READE to control the data output buffer
5
.
When data is read from the SDRAM, the read command signal READE is provided to the control unit
10
, where the read command READE transits a “low” level to a “high” level. Upon reception of the READE signal, the data output buffer control unit
10
generates the control signal DOEB which transits from the “high” to “low” level in synchronization with the clock signal CLK, for enabling the data output buffer
5
after a preset time interval. While the control signal DOEB from the data output buffer control unit
10
is held at the “low” level, the data output buffer
5
is enabled to provide data DOUT from the SDRAM to the I/O pad
1
. When the read operation ends, the “READE” signal is switched from the “high” to “low” level so that the data output buffer control unit
10
switches the control signal DOEB from the “low” to “high” level after a preset time period, for disenabling the data output buffer
5
. Accordingly, the data output buffer
5
is brought into a “high impedance” state.
However, the related art circuit for controlling input/output buffer has various disadvantages. For example, in the related art circuit for controlling input/output buffers, there is an unnecessary induction of a switching current at the data input buffer caused by output data fed back to the data input buffer when the data output buffer outputs data to the I/O pad in a read operation. The feedback becomes greater as a plurality of data is continuously read.
The above references and/or discussion are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to substantially obviate at least one or more of the problems of the related art.
An object of the present invention is to prevent generation of a switching current.
Another object of the present invention is to eliminate unnecessary switching current.
A further object of the present invention is to reduce power consumption.
The present invention can be achieved in a whole or in parts by a circuit for controlling data input/output buffers includes a semiconductor circuit, comprising an input/output pad for at least one of input and output of data; a data input buffer for receiving data from the input/output pad; a data output buffer for output of the data to the input/output pad; and, a controller that provides a control signal to control the data input and output buffers such that only one of the data input buffer and the data output buffer is enabled during a prescribed operation.
The present invention can be also achieved in a whole or in parts by a data input buffer comprising a plurality of transistors coupled in series, and a first transistor having first and second electrodes and a control electrode, wherein the first electrode of the first transistor is coupled to a serial connection within the plurality of transistors coupled in series.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 4758985 (1988-07-01), Carter
patent: 4857763 (1989-08-01), Sakurai et al.
patent: 4987319 (1991-01-01), Kawana
patent: 5300835 (1994-04-01), Assar et al.
patent: 5898320 (1999-04-01), Li et al.
patent: 5949254 (1999-07-01), Keeth
patent: 6124737 (2000-09-01), Lan et al.

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