Electronic digital logic circuitry – Threshold
Reexamination Certificate
2001-12-18
2003-11-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Threshold
C326S046000, C327S199000
Reexamination Certificate
active
06646464
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an &agr;(alpha)-ray assurance technology in semiconductor devices. More particularly, this invention relates to a technology for preventing an error operation of flip-flop circuits due to the &agr;-rays, and provides flip-flop circuits having high &agr;-ray resistance, a semiconductor device, a designing method of the semiconductor device and a database for the designing method.
A flip-flop type latch circuit has widely been employed as a circuit for temporarily holding data or a signal level in semiconductor integrated circuits, particularly in logical integrated circuits.
As an amount of the charge built up inside a flip-flop circuit becomes smaller with microstructuring of semiconductor elements in a semiconductor integrated circuit, inversion of a potential due to the charge generated by the &agr;-rays is more likely to develop. The semiconductor integrated circuit uses a large number of flip-flop circuits, in particular. Since the number of constituent elements is large, too, the flip-flop circuit is constituted in most cases by the smallest constituent devices. Once the potential is inverted, it continues outputting error values until a normal value is acquired next, and the influences are great, too. For this reason, the error operation resulting from the &agr;-rays is more likely to occur. To cope with the &agr;-rays, proposals have been made in the past to positively apply a capacitor to internal nodes of the flip-flop circuit or to intentionally increase parasitic capacitance (refer to JP-A-10-199996).
SUMMARY OF THE INVENTION
In the semiconductor integrated circuit, the size of the semiconductor element (hereinafter also called merely the “element”) and the operation frequency are substantially inversely proportional to each other. Therefore, to suppress the increase of power consumption due to the increase of the operation frequency, the flip-flop circuit is designed in many cases in such a fashion that parasitic capacitance of internal nodes decreases in proportion to miniaturization of the semiconductor elements. On the other hand, the amount of the charge that is generated when the &agr;-rays pass through the flip-clop circuit decreases with miniaturization of the elements, but the amount of its decrement is smaller than the amount of decrease of the parasitic capacitance of the internal nodes brought forth by miniaturization of the element.
It has been found that the &agr;-ray assurance technology that applies the capacitance to the internal node involves the following problems. As miniaturization of the devices proceeds, a capacitor of a relatively greater capacitance becomes necessary inside the flip-flop circuit, and the operation speed, power consumption and an occupying area are sacrificed. Whenever the size of devices constituting the flip-flop circuit or the value of a power source voltage used is changed, the capacitance to be imparted to the internal nodes of the flip-flop circuit must be estimated once again and this becomes a large burden to design.
MOS transistors having a high threshold value are often used to constitute a logic circuit in CMOS-LSI to reduce a standby current. When the threshold value of the MOS transistors is raised, however, driving power drops and ON resistance becomes great. Consequently, it becomes more difficult for the node, whose potential has changed due to the &agr;-rays, to return to the original potential. In this case, a logic gate of a next stage is more likely to respond to the change before the return of the potential and to cause an error operation. The power source voltage of LSI has been lowered, but the error operation becomes more likely to occur when the power source voltage drops and driving power of the MOS transistors drops, or when the amount of the charge built up in the internal node decreases.
It is an object of the present invention to provide a semiconductor integrated circuit technology that can ensure &agr;-ray resistance or &agr;-ray immunity of flip-flop circuits even when semiconductor elements are miniaturized.
It is another object of the present invention to provide a semiconductor integrated circuit technology that does not require to design once again a circuit construction of flip-flop circuits or capacitance of internal nodes in accordance with the size of semiconductor elements or with a value of a power source voltage to ensure &agr;-ray resistance of the flip-flop circuits even when the semiconductor elements are miniaturized or when the value of the power source voltage is changed.
It is still another object of the present invention to provide a semiconductor integrated circuit technology that can prevent the error operation resulting from the &agr;-rays of flop-flop circuits even when a threshold value of MOS transistors is raised or when the value of the power source voltage used becomes lower.
These and other objects and novel features and advantages of the present invention will become more apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.
Typical aspects of the present invention disclosed herein are as follows.
According to an aspect of the present invention, a data hold circuit comprises at least three flip-flop circuits for inputting the same signal, and a majority logic circuit for outputting a signal in accordance with a logic value of the majority of the outputs of the flip-flop circuits. Therefore, even when an &agr;-ray passes through any of the flip-flop circuits and the output changes, the other flip-flop circuits can keep a correct output signal and reliability of the circuit can be improved. Moreover, unlike a flip-flop circuit that is so constituted as to keep a level by means of only the charge of capacitor, the data hold circuit of this invention can reliably avoid the error operation resulting from the &agr;-ray even when the elements are miniaturized.
In the aspect of the present invention described above, the three or more flip-flop circuits described above are so constituted as to acquire input signals on the basis of mutually different clock signals synchronized with one another. In consequence, the data hold circuit can keep a correct output signal even when any noise overlaps with the clock signals or when an error pulse occurs due to the incidence of the &agr;-rays to clock amplifiers and any of the flip-flop circuits acquire an error data, and reliability of the circuit can be further improved.
In the construction described above, two flip-flops among the three flip-flop circuits acquire the input signals on the basis of mutually different two clock signals synchronized with each other, and the other one flip-flop circuit is so constituted as to use the two clock signals as its input and to acquire its input signal on the basis of an output signal of a logic circuit whose output changes in accordance with the normal change of these clock signals. This construction can prevent the error operation of the flip-flop circuits due to the noise overlapping with the clock signals and due to the incidence of the &agr;-rays to the clock amplifier, and can decrease the number of signal lines for supplying the clock signals. The clock signal for the flip-flop circuits may be used in common, provided that the influences of the noise and the &agr;-rays on the clock signals can be neglected.
The flip-flop circuit described above is a flip-flop circuit with a diagnosis function that is equipped with a scan-in terminal and a scan-out terminal for test data. Therefore, it is possible to diagnose each of the majority logic circuit and the flip-flop circuit.
In two of the three flip-flop circuits described above, switch means for switching common scan-in data and the output from the scan-out terminal of the other flip-flop circuit is disposed as a pre-stage circuit of the scan-in terminal. When the common scan-in data is selected, the number of scan-in data can be decreased and a general logic circuit among the flip-flops can be efficiently diagnosed. When th
Cho James
Hitachi , Ltd.
Tokar Michael
LandOfFree
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