Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2006-02-03
2008-12-02
Peyton, Tammara R (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S003000, C710S029000, C710S033000, C710S038000, C710S051000, C710S055000, C710S062000, C714S028000, C714S037000, C714S039000, C713S400000
Reexamination Certificate
active
07461186
ABSTRACT:
The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by the output unit.
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patent: 7058855 (2006-06-01), Rohfleisch et al.
patent: 2005/0081113 (2005-04-01), Beard et al.
Gregorius Peter
Gu Zheng
Rickes Thomas
Schledz Ralf
Streibl Martin
Infineon - Technologies AG
Patterson & Sheridan L.L.P.
Peyton Tammara R
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