Data handling system for handling data transfers between a cache

Details Data handling system for handling data transfers between a cache Data handling system for handling data transfers between a cache

1983-12-05

1987-02-24

Thomas, James D.

Boots, shoes, and leggings

G06F 1300, G06F 1200

Patent

active

046462376

ABSTRACT:
In a data handling system having one or more processors, a cache memory associated with each processor and a main memory unit, each cache memory is divided into an equal number of portions, and the main memory is divided into a corresponding number of portions. A data transfer bus is provided between each group of cache memory portions and the corresponding portion of main memory such that each group of cache memory portions corresponds to only a portion of main memory. Each data transfer bus in independently controlled such that the rate of data transfers for the system as a whole is increased.

REFERENCES:
patent: 3593299 (1971-07-01), Driscoll et al.
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 4384327 (1983-05-01), Conway et al.
patent: 4387441 (1983-06-01), Kocol et al.
patent: 4424561 (1984-01-01), Stanley et al.
patent: 4445172 (1984-04-01), Peters et al.
patent: 4464717 (1984-09-01), Keeley et al.
patent: 4468729 (1984-09-01), Schwartz

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