Static information storage and retrieval – Read/write circuit – Sipo/piso
Reexamination Certificate
2007-04-21
2008-10-14
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Read/write circuit
Sipo/piso
C365S220000, C365S221000, C365S194000, C365S236000, C365S233110, C365S233120, C365S233140, C341S147000, C341S101000
Reexamination Certificate
active
07436725
ABSTRACT:
A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing the address after the trigger signal. A hexadecimal counter counts a clock that is faster than the divided clock as the counted number circulates every one period of the divided clock . A trigger information latch latches the counted number of the counter when the trigger signal arrives and provides it to a MUX. The MUX selects data in a pair of the parallel data provided at first and second inputs I1and I2to produce rearranged parallel data bits according to the latched counted number. A parallel to serial converter receives the rearranged parallel data to convert it to serial data according to the clock.
REFERENCES:
patent: 4692886 (1987-09-01), Miki et al.
patent: 7295139 (2007-11-01), Fujisawa
patent: 2007/0247927 (2007-10-01), Miki
patent: 2007-295132 (2007-11-01), None
Bucher William K.
Tektronix International Sales GmbH
Tran Andrew Q
LandOfFree
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