Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2008-07-29
2010-10-26
Cleary, Thomas J (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S052000, C710S057000, C710S110000, C710S306000
Reexamination Certificate
active
07822906
ABSTRACT:
A bridge capable of preventing data inconsistency without degrading system performance is provided, in which a buffering unit comprises a plurality of buffers, a first master device outputs a flush request to flush the buffering unit, and a flush request control circuit records the flushed buffer(s) in the buffering unit when receiving the flush request and outputs a flush acknowledge signal to indicate to the first master device that the buffering unit has been flushed when all the plurality of buffers have been flushed once after the flush request has been received.
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Fan Jin
Xu Xiaohua
Cleary Thomas J
Thomas Kayden Horstemeyer & Risley
Via Technologies Inc.
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