Data error detection and correction circuit

Details Data error detection and correction circuit Data error detection and correction circuit

1984-08-24

1987-02-24

Smith, Jerry

Excavating

371 37, G06F 1108

Patent

active

046463038

ABSTRACT:
In a digital system, there is provided a circuit for detecting and correcting errors in a group of data using Reed-Solomon codes. The group of data is first stored in a memory, and syndromes of the data are produced by a syndrome calculation circuit and fed to an internal data bus. A first data conversion circuit converts the syndromes on the internal data bus into logarithmic values and a multiplier-divider circuit executes multiplication or division of the data on the internal data bus by addition and subtraction operations of the logarithmic values. A second data conversion circuit converts antilogarithmically data from the multiplier-divider circuit, and an addition and subtraction circuit executes addition or subtraction of the data from the second data conversion circuit. An error detection circuit detects whether a single error exists in the group of data in accordance with the syndromes, and an error detection signal representing existence of error and an error location signal representing error location are produced. An address control circuit addresses the memory in accordance with the error detection signal and the error location signal so that the memory outputs an error data. A data correction circuit adds one of the syndromes representing amount of data error on the internal data bus to the error data outputted from the memory to produce its correct data. A double data error can be detected and corrected using Reed-Solomon codes in a similar manner.

REFERENCES:
patent: 4142174 (1979-02-01), Chen
patent: 4413339 (1983-10-01), Riggle
patent: 4564945 (1986-01-01), Glover

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