Data erasing and re-writing circuit for use in microcomputer int

Details Data erasing and re-writing circuit for use in microcomputer int Data erasing and re-writing circuit for use in microcomputer int

1991-08-26

1993-09-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

With shift register

365218, 365233, 365236, G11C 700

Patent

active

052435610

ABSTRACT:
Data in an EEPROM contained in a microcomputer integrated circuit device is erased and re-writing. Upon a detection of a start bit of the data, data of a plurality of bits is accepted in a shift register in response to a clock signal applied from a synchronization circuit. A counter counts clock signals up to the number corresponding to the data of a plurality of bits to inhibit data writing in the shift register. The data accepted in the shift register is temporarily stored as bit parallel data of a plurality of bits in a receiving buffer and selected by a selector to be applied to the EEPROM. The data is written, by a write control circuit, at an address in the EEPROM designated by an address counter.

REFERENCES:
patent: 4321695 (1982-03-01), Redwine et al.
patent: 4506348 (1985-03-01), Miller et al.
patent: 4866616 (1989-09-01), Takeuchi et al.
patent: 4987559 (1991-02-01), Miyauchi et al.
"Z80 Microprocessor Technology, Hardware, Software and Interfacing", 1986, Bignell et al., pp. 203-219.

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