Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-07-10
2007-07-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S805000, C714S819000, C711S108000, C365S049130
Reexamination Certificate
active
10616958
ABSTRACT:
A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an incoming CAM or TCAM word to produce an encoded CAM or TCAM word such that a one-bit mismatch between a comparand and the incoming CAM or TCAM word results in at least a M-bit mismatch between said encoded CAM or TCAM word and a similarly encoded comparand, a circuit for precharging a match line to a predetermined state before a comparison between the encoded CAM or TCAM word and said similarly encoded comparand and a memory storage location for storing the encoded CAM or TCAM word.
REFERENCES:
patent: 6842359 (2005-01-01), Hata et al.
patent: 6944710 (2005-09-01), Regev et al.
patent: 6975526 (2005-12-01), Regev et al.
patent: 7002823 (2006-02-01), Ichiriu
patent: 7017089 (2006-03-01), Huse
Abraham Esaw
De'cady Albert
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