Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-10-13
2002-07-23
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C341S058000, C341S059000, C341S100000, C341S101000
Reexamination Certificate
active
06425107
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
The present invention generally relates to the transmission of data over a serial data link and more particularly to encoding methods and apparatus for generating DC balanced, run length limited codes for transmission over a serial data link and a decoder for decoding such codes.
Numerous applications exist in which it is desirable to transmit data over a high speed serial data link. Well known problems must be overcome, however, when transmitting data over serial data links at high speed. To maintain a high signal to noise ratio, differential transmitters and receivers are often employed at the transmitting and receiving ends of the serial link. It is well known that it is desirable to maintain the transmitted binary signal generally in a DC balanced state to maintain good common mode rejection characteristics at the receiver. DC balance is maintained by transmitting approximately the same number of binary 1s as 0s over the link. This would not typically occur if data were just randomly transmitted over the serial data link. To obtain a DC balanced signal for transmission over a serial link it is known in the art that encoders and decoders may be employed to assure that a balanced condition is maintained over the link. If transmissions over the serial link are imbalanced (i.e. more binary 1's than 0's or more 0's than 1's) a DC offset may be induced on the serial link which can interfere with the ability of a differential receiver to properly decode the binary digits.
When transmitting data at high speeds over a serial data link it is often impractical or not desirable to provide a separate clock signal for data recovery at the receiver since clock skew may occur. Additionally, it is often desirable to minimize the number of backplane or data link signals and the provision of a separate clock signal necessarily increases the signal count. For this reason, a clock signal is sometimes recovered from the serially transmitted data using a phase locked loop at the receive end of the serial data link. To maintain proper operation of a phase locked loop, however, the input signal to the phase locked loop must exhibit sufficient transitions for the phase locked loop to maintain a lock on the input data frequency. If the received data, for example, comprises a long string of logic 1s or 0s, the absence of transitions renders clock recovery difficult. For this reason, run length limited encoding techniques are employed. A run length limited (RLL) code is an encoded character which has a maximum number of logic 0s or 1s in a row. For example, a digital signal with a run length limit of 5 has a maximum of five consecutive logic 0s or 1s. It is known to select run length limited codes so as to maintain the run length over successive characters. The use of such run length limited encoding technique maintains sufficient clocking transitions to permit clock recovery and recovery of the data stream at the receiver.
A number of encoding techniques have been developed to address the problems associated with the maintenance of DC balance and data stream synchronization using RLL codes. One such technique is disclosed in U.S. Pat. No. 4,486,739 entitled Byte Oriented DC Balanced (0,4) 8B/10B Partitioned Block Transmission Code. The encoding circuit therein disclosed partitions an 8 bit byte of information into 5 bit and 3 bit sub-blocks for encoding purposes. The 5 bit and 3 bit blocks are separately encoded while maintaining DC balance across all block and sub-block boundaries.
It would therefore be desirable to be able to provide a simple, cost effective DC balanced encoder/decoder with a short run length limit to provide improved data transmission and clock recovery over a serial data link.
BRIEF SUMMARY OF THE INVENTION
A data encoding circuit for generating encoded data for transmission over a high speed serial link is disclosed along with a decoding circuit for decoding such encoded data. The encoding/decoding circuits provide transition density and DC balance. A receiver uses a phase locked loop to resynchronize bits in the data transmission stream and hence benefits from the transitions between logic 1s and logic 0s.
In the illustrated embodiment, the encoding circuit employs two encoders in parallel. Each encoder receives an 8 bit input word and generates a 10 bit run length limited output word. Each encoder includes at least one table or map which is employed to convert the eight bit input word to an encoded 10 bit run length limited output word. The encoded output words are selected for use in the tables based on transition density and DC balance criteria. Hence, a predefined transition density is assured.
To obtain the necessary 256 entries for an eight bit input word, all possible balanced (equal number of logic 0 and logic 1 bits) ten bit words are used. However, since fewer than 256 balanced ten bit words exist, a number of ten bit words are employed which are imbalanced by only two bits. DC imbalance is tracked using a weight variable. The 10 bit words in the tables are chosen such that the sign of the imbalance is predictable when imbalance occurs, i.e., it will always be in favor of a particular logic level. When an imbalanced transmission occurs, it is detected. Any subsequent balanced 10 bit word is transmitted normally. However, the next imbalanced ten bit word is inverted prior to transmission to mitigate the detected imbalance. The above described process operates continuously such that DC imbalance is never greater than two bits at any character boundary at the receiver input.
The encoded 10 bit run length limited words are transmitted over the serial link within a packet which includes a preamble, a sync field, a data field and a postamble. The postamble is employed to assure that DC balance is maintained at the completion of the transmission of each packet over the serial link.
The decoding circuit includes tables for mapping the ten bit words, including complimentary imbalanced pairs of words, to the original input eight bit words. In a preferred embodiment, the decoding circuit includes two decodes which operate in parallel. Each decoder performs a verification operation to determine whether the received ten bit code is valid, i.e., contained in the decoder table.
REFERENCES:
patent: 3577142 (1971-05-01), McMillin
patent: 3594360 (1971-07-01), Gaeth
patent: 3798635 (1974-03-01), Candiani
patent: 4309694 (1982-01-01), Henry
patent: 4387364 (1983-06-01), Shirota
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 4520346 (1985-05-01), Shimada
patent: 4523181 (1985-06-01), Tazaki et al.
patent: 4665517 (1987-05-01), Widmer
patent: 4675650 (1987-06-01), Coppersmith et al.
patent: 4677421 (1987-06-01), Taniyama
patent: 4725815 (1988-02-01), Mitchell et al.
patent: 4728929 (1988-03-01), Tanaka
patent: 4779072 (1988-10-01), van Gestel
patent: 4916605 (1990-04-01), Beardsley et al.
patent: 5122912 (1992-06-01), Kanota et al.
patent: 5200979 (1993-04-01), Harris
patent: 5319782 (1994-06-01), Goldberg et al.
patent: 5396239 (1995-03-01), McMahon et al.
patent: 5659310 (1997-08-01), McLaughlin
patent: 5703580 (1997-12-01), Ko
patent: 5742243 (1998-04-01), Moriyama
patent: 5757293 (1998-05-01), McLaughlin
patent: 5774078 (1998-06-01), Tanaka et al.
patent: 6002718 (1999-12-01), Roth
J.M. Griffiths, Binary Code Suitable for Line Transmission, Post Office Research Station, Dollis Hill, London NW2, England, pp. 79-81, Jan. 28th, 1969.
T. Horiguchi and K. Morita, An Optimization of Modulation Codes in Digital Recording, Central Research Lab, Nippon Electric Co., Ltd., Kawasaki, Japan; IEEE Transactions on Magnetics, vol. MAG-12, No. 6, pp. 740-747, Nov. 1976.
R. G. Kiwimagi, Encoding/Decoding for Magnetic Record Storage Apparatus, IBM Technical Disclosure Bulleting, vol. 18, No. 10, pp. 3147-3149, Mar. 1976.
W.W. Peterson, and D.T. Brown, Cyclic Codes for Error Detection, Proceeding of the IRE, pp. 228-234; (Jan. 1961).
Paul F. Nee et al., Method for Com
Caldara Stephen A.
Sluyski Michael
Strouble Raymond L.
Fujitsu Network Communications, Inc.
Moise Emmanuel L.
Weingarten Schurgin, Gagnebin & Lebovici LLP
LandOfFree
Data encoder/decoder for a high speed serial link does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data encoder/decoder for a high speed serial link, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data encoder/decoder for a high speed serial link will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2818708