Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2002-03-27
2003-06-10
Wong, Don (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C345S060000, C315S169100
Reexamination Certificate
active
06577071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a drive circuit of a plasma display device, and more particularly to a data driver having a function that reduces noise attributed to display data, generated at the time of electrode voltage switching.
2. Related Art
In a plasma display of the surface discharge type, row and column electrodes are provided on two glass substrates, respectively, a dielectric layer being provided above the row electrodes of the row electrode glass substrate and a phosphor layer being provided over the column electrodes of the column electrode glass substrate having partition walls, a discharge space being provided between two substrates facing each other and a gas being sealed between the above-mentioned two substrates, which form display panel having a planar matrix structure, in which the row electrodes and the column electrodes are independently driven, so as to cause a plasma discharge at the intersection (cell) between driven row and column electrodes, thereby exiting the phosphor layer provided on the column electrodes so that it emits light. In the case of a display panel that produces a color display, each column electrode is made up of electrodes for three colors having phosphor layer for red (R), green (G), and blue (B), each of the color electrodes for each column being driven separately so as to produce a color display having a plurality of colors.
Additionally, as the row electrodes, X electrodes and electrodes are provided. The X electrodes provided in common for each row and the Y electrodes provided for each row are alternately disposed. In the above-noted case, when driving these electrodes, a voltage pulse is applied alternating between the X and Y electrodes, thereby causing a discharge that reverses the electrode each half cycle. This type of driving method is known as AC drive method.
In an AC plasma display panel (AC-PDP) as described above, once a discharge occurs between the electrodes of each cell, the electrons and ions generated in the discharge space are accumulated on the phosphor layer, thereby forming a wall charge, after the formation of which it is possible because of the action of the wall charge to cause a discharge with a low voltage, and it is possible to sustain the discharge by alternating this low voltage each half cycle. This function is called as a memory function, the discharge sustained by the low voltage based on the memory function is called as sustaining charge.
In an AC-PDP, in order to achieve a gradation representation, the video signal during a single field period is divided into a plurality of sub-fields, the time (number of times) during which a discharge is sustained for each sub-field being controlled. More specifically, for each sub-field, after resetting, by assigning a sustaining discharge period that increases in proportion to 2
n
, for example, the greater is the number of sustaining discharges made, the brighter will be the light from a cell, thereby performing a gradation representation.
The configurations of an AC-PDP and a conventional data driver circuit and the operation thereof are described below.
FIG. 9
of the accompanying drawings, is a block diagram showing the configuration of an AC color PDP to which the prior art and the present invention could be applied,
FIG. 10
is a drawing showing the configuration of a data driver circuit of the past,
FIG. 11
is a timing diagram showing the format of the display data input to the data driver circuit, and
FIG. 12
is a flowchart illustrating the output operation of the data driver circuit.
As shown in
FIG. 9
, an AC-PDP
100
has a plurality of data driver circuits
101
A,
101
B,
101
C, . . . ,
101
E, an AC type plasma display panel (AC-PDP)
102
, scan driver circuits
103
A, . . . ,
103
C, a format conversion circuit
104
, a drive signal generating circuit
105
, and a high-voltage drive circuit
106
.
The data driver circuits
101
A,
101
B,
101
C, . . . ,
101
E, which are formed by integrated circuits, receive from the format conversion circuit
104
a prescribed number (n) of serial display data signals at a time corresponding to the N column electrodes, and output data in parallel to the column electrodes for each scan period in response to a parallel latch control signal from the drive signal generating circuit
105
.
The AC-PDP
102
is an AC-driven type plasma display panel, which performs drive in accordance with a sub-field sequence using a memory function, and has a matrix electrode arrangement having M rows of row electrodes and N columns of column electrodes (data electrodes) corresponding to the three colors R, G, and B for each of the columns. The scan driver circuits
103
A, . . . ,
103
C, which are formed by integrated circuits, in response to row drive signals from the drive signal generating circuit
105
for each prescribed number of rows, sequentially output scan signals to the M rows of row electrodes.
The format conversion circuit
104
converts the format of video data having the three colors R, B, and G by using frame memories
111
, and the converted three colors R, G, and B signals are sequentially arranged for each column, and the serial display data signals are output from the format conversion circuit
104
.
The drive signal generating circuit
105
, in response to a vertical synchronization signal included in the video data signal detected by a vertical synchronization signal detection circuit (not shown in the drawing), according to a prescribed sequence for each field, generates row and column drive signals, and supplies these signals to the data driver circuits
101
A,
101
B,
101
C, . . . ,
103
E, and to the scan driver circuits
103
A, . . . ,
103
C. The high-voltage drive circuit
106
, in response to a drive signal from the drive signal generating circuit
105
, supplies a high-voltage to each of the data driver circuits
101
A,
101
B,
101
C, . . . ,
101
E.
A data driver circuit
101
of the past, as shown in
FIG. 10
, generally comprises an n-stage shift register circuit
11
, a parallel latch circuit
12
with n circuits, n output control logic gates G
1
, G
2
, G
3
, G
4
, . . . , Gn, and n high withstand voltage CMOS (complementary metal oxide semiconductor) drivers B
1
, B
2
, B
3
, B
4
, . . . , Bn. In the AC-PDP
102
as shown in
FIG. 10
, the electrode structure for each of the three colors R, G, and B in each column is abbreviated to just a single data electrode DL that is shown.
The shift register circuit
11
is formed by an n-stage shift register, and acts to shift the serial display data signal DS input from the frame memory
111
for each scan period at a time. The parallel latch circuit
12
latches the outputs from the n-stage shift register of the shift register circuit
11
in response to a parallel latch control signal &PHgr; from the drive signal generating circuit
105
.
The output control gate circuits G
1
, G
2
, G
3
, G
4
, . . . , Gn, in response to an output control signal OS from the drive signal generating circuit
105
, output signals Q
1
, Q
2
, Q
3
, Q
4
, . . . , Qn from the parallel latch circuit
12
for each scan period. The high-voltage CMOS drivers B
1
, B
2
, B
3
, B
4
, . . . , Bn, by using the high-voltage supply Vd from the high-voltage drive circuit
106
, convert the parallel signals Q
1
, Q
2
, Q
3
, Q
4
, . . . , Qn from the output control gate circuits G
1
, G
2
, G
3
, G
4
, . . . , Gn to data signals O
1
, O
2
, O
3
, O
4
, . . . , On, which are high-voltage write pulses, these being output to the data electrodes of the AC-PDP
102
.
The output states of the data driver circuit
111
, as shown in
FIG. 11
, have two forms. In
FIG. 11
, FIG.
11
(
a
) shows the case of 1-bit data output, and FIG.
11
(
b
) shows the case of 3-bit data output.
In the case of 1-bit data output, as shown in FIG.
11
(
a
), the input data DS are repeatedly arranged in the sequence of R, G, and B, the shift register circuit
11
shifts these data DS at each rising edge of the shift clock, and when the final shift
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