Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-11-24
2003-05-06
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S083000
Reexamination Certificate
active
06559680
ABSTRACT:
BACKGROUND
This invention relates generally to domino circuits.
A static CMOS gate is a fully complementary logic gate with P and N-channel (i.e., p-channel and n-channel metal oxide semiconductor) devices configured to implement a desired logic function. A dynamic complementary metal oxide semiconductor (CMOS) gate includes an N-channel device logic structure having a pre-charge or output node precharged to the supply voltage with a single clocked P-channel device. The output node is conditionally discharged (evaluated) by a set of devices forming the logic structure, coupled to external ground.
The clocked P-channel device has its gate coupled to an input clock signal. When the input clock signal is active, the output node is “precharged” through a P-channel device to the supply voltage. When the clock input is inactive, the output node is conditionally discharged (evaluated) through the set of devices forming the logic structure, to external ground. The logic structure may implement a logic function such as a NAND or a NOR logic function as examples.
Dynamic or domino logic circuits are dynamic because operation of the circuit is controlled dynamically by an input clock signal. Domino logic units are typically arranged in a plurality of domino stages, each stage having logic cells, such as NAND gates or NOR gates as examples, with each stage separated by an inverting stage. In this arrangement, an input signal applied to the first stage while the clock signal is active, triggers operation of the remaining stages in sequence. This yields a domino-like signal propagation effect within the logic unit.
During the evaluation phase, the inputs to the set of devices forming the logic structure only change from non-active to an active state. Otherwise, the output node may be corrupted without P-channel devices to pull the output node back up. Inverting stages are provided between each logic stage to facilitate proper precharging or evaluating of the individual domino circuits active during the precharge phase.
Referring to
FIG. 4
, a single stage NAND gate domino circuit
10
includes a single P-channel device
12
a
in combination with a set of N-channel devices
14
forming a logic structure. A keeper
16
may include an inverter and a P-channel transistor. The keeper offsets any charge leakage that might occur at the output node when the N-channel devices
14
of the logic structure are inactive. A domino NAND gate may be referred to as a “clocked” domino gate because the input clock signal is connected to an N-channel device
12
b
in series with the N-channel devices of the logic structure. The single N-channel device
12
b
connected to the clock signal selectively blocks a power dissipation path between the external power supply and external ground during the precharge phase.
In use, dynamic or domino logic circuits operate in phases including a precharge phase and an evaluate phase. During the precharge phase, the transistors of the logic structure of the domino circuit are precharged. During the evaluate phase, input signals may be applied to the gates of each of the transistors of the logic structure and the clock signal is active.
As feature size and external power supplies are scaled as a result of advances in CMOS process technology, a significant decrease in the charge at the input and output nodes of domino circuits may result. This decrease in node charge may lead to an increase in soft error rates (SER) caused by cosmic radiation and packaging materials.
During an SER event, domino circuits may generate errors while holding a high or active level at the precharge node. Noise immunity may be improved by adding a P-channel keeper. Although the robustness of a domino gate against soft errors may be enhanced by increasing the size of the keeper, this eventually leads to performance degradation. This may be due in part because contention may arise between the keeper and the N-channel devices of the logic structure. This degradation may be significant, in large fan-in domino topologies for example, as the effective width of the N-channel devices of the structure is small.
Thus, there is a continuing need for better ways to decrease the soft error rates of domino circuits.
SUMMARY
In accordance with one aspect, a domino circuit includes an output node and an input transistor coupled to the output node. A charge source is coupled to the node and the transistor to selectively charge the node depending on the signal applied to the transistor.
Other aspects are set forth in the accompanying detailed description and claims.
REFERENCES:
patent: 3551693 (1970-12-01), Burns et al.
patent: 5223834 (1993-06-01), Wang et al.
patent: 5612638 (1997-03-01), Lev
patent: 5852373 (1998-12-01), Chu et al.
patent: 6002292 (1999-12-01), Allen et al.
patent: 6025739 (2000-02-01), Campbell et al.
patent: 6043674 (2000-03-01), Sobelman
patent: 6052008 (2000-04-01), Chu et al.
patent: 6204696 (2001-03-01), Krishnamurthy et al.
Bhushan Bharat
Joshi Vivek
Chang Daniel
Intel Corporation
Trop Pruner & Hu P.C.
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