Data-driven information processing device and method to...

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules

Reexamination Certificate

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C709S245000, C709S238000

Reexamination Certificate

active

07133959

ABSTRACT:
An address calculation unit calculates a plurality of addresses corresponding to a plurality of data included in a data packet. A first bank memory access unit accesses a first bank memory according to a first address calculated by the address calculation unit. Simultaneously, a second bank memory access unit accesses a second bank memory according to a second address calculated by the address calculation unit. A packet reconstruction unit reconstructs the data packet according to the results of access by the first and second bank memory access units. Accordingly the processing rate of the data packet including a plurality of data is increased.

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patent: 5905725 (1999-05-01), Sindhu et al.
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patent: 6757791 (2004-06-01), O'Grady et al.
patent: 5-233854 (1993-09-01), None
patent: 9-114664 (1997-05-01), None

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