Data descrambling in semiconductor memory device

Details Data descrambling in semiconductor memory device Data descrambling in semiconductor memory device

1991-07-31

1992-08-04

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365 51, 365201, G11C 506, G11C 700

Patent

active

051365430

ABSTRACT:
A semiconductor memory device comprises a plurality of bit line pairs and an input/output line pair. Each bit line pair comprises first and second bit lines supplied with complementary data, and the input/output line pair comprises first and second input/output lines supplied with complementary data. A switching circuit is provided on each bit line pair. Each switching circuit, in response to a control signal according to an address signal, respectively couples the first and the second bit lines to the first and the second input/output lines, or inversely, respectively couples the first and the second bit lines to the second and the first input/output lines.

REFERENCES:
patent: 4866676 (1989-09-01), Crisp et al.
patent: 4916661 (1990-04-01), Nawatti et al.
Kanz et al., "A 256K DRAM with Descrambled Redundancy Test Capability", 1984 IEEE International Solid-State Circuits Conference, Feb. 24, 1984, pp. 272-273, 352.
Yoshihara et al., "A Twisted Bit Line Technique for Multi-Mb DRAMs", 1988 IEEE International Solid-State Circuits Conference, Feb. 19, 1988, pp. 238-239.

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