Data decoding method and apparatus and receiver and...

Details Data decoding method and apparatus and receiver and... Data decoding method and apparatus and receiver and...

2007-10-09

2007-10-09

Torres, Joseph D. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S795000

Reexamination Certificate

active

10895324

ABSTRACT:
A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a rate dematch apparatus to a decoder. The information bits are switched directly to the decoder.

REFERENCES:
patent: 6304995 (2001-10-01), Smith et al.
patent: 6665357 (2003-12-01), Somayazulu
patent: 6738948 (2004-05-01), Dinc et al.
patent: 6813742 (2004-11-01), Nguyen
patent: 6996767 (2006-02-01), Chang et al.
patent: 2002-9633 (2002-01-01), None
patent: 2002-308863 (2002-07-01), None
3GPP—3rd Generation Partnership Project: Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD) (Release 5); TS 25.212, V5.4.0, pp. 1-74 (2003).

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