Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1998-02-27
2001-02-13
Pham, Chi H. (Department: 2731)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S262000, C714S795000
Reexamination Certificate
active
06188735
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data decoding apparatus and method, and more particularly, to a data decoding apparatus and method for reducing hardware size by decoding data using a single channel maximum likelihood decoder in a digital recording/reproducing apparatus having a partial-response class 4 (PR4) or extended-partial response class 4 (E
n
PR4) channel.
Techniques related to a Partial Response Maximum Likelihood (PRML) have been developed, including a Viterbi decoding processing, as methods for increasing recording density by a signal processing without greatly changing characteristics of a conventional recording and reproducing apparatus.
FIG. 1
is a block diagram of a digital video cassette recorder (DVCR) having a PR4(1, 0, −1) channel. In
FIG. 1
, a Non-Return-to-Zero-Inversion (NRZI) converter
102
converts an input signal into an NRZI code represented by 1 or −1. A precoder
108
converts the NRZI code into an interleave NRZI code. Here, the NRZI converter
102
and the precoder
108
are constructed to have a 1/1+D characteristic, where D refers to a 1-bit delay (unit delay) of recording data. In the NRZI converter
102
or the precoder
108
having a 1/l+D structure, an input signal and a signal delayed by a delay element
106
or
112
are input to an XOR gate
104
or
110
and the XOR-performed signal is fed back to the delay element.
A reproducing amplifier
116
of a reproducing system amplifies a reproduction signal through a channel
114
having a 1-D characteristic, i.e., a differential characteristic. At this time, the amplified reproduction signal is a PR(+1, −1) mode signal. An equalizer
118
compensates for waveform distortion and amplitude distortion of the signal amplified in the reproducing amplifier
116
. A channel demodulator
120
having a 1+D characteristic, i.e., an integral characteristic, converts a PR(+1, −1) mode signal output from the equalizer
118
into a PR4(+1, 0, −1) mode signal. In other words, the channel demodulator
120
includes an adder
124
and a delay
122
and has the 1+D characteristic inverse to the 1/1+D characteristic of the precoder
108
, so that noise characteristics are improved and the aperture ratio of an eye pattern is decreased. A timing detector
140
detects timing of the reproduction signal equalized in the equalizer
118
using an internally installed phase locked loop (PLL) and outputs driving clocks required for the equalizer
118
and the maximum likelihood decoder
126
.
Here, since the recording system of the digital recording/reproducing apparatus having the PR
4
channel includes two delays, the reproducing system requires four (2
2
) 4-state Viterbi decoders. However, in the DVCR, since two (1+D) channels are interleaved, 2-state Viterbi decoders are necessary. In other words, the maximum likelihood decoder
126
shown in
FIG. 1
is constructed such that two state detectors
130
and
132
and two Viterbi decoders
134
and
136
, performing the same operation, are connected in parallel, respectively. A demultiplexer
128
and a multiplexer
138
operate according to a driving clock output from a timing detector
140
. Decoded data is output from the multiplexer
138
.
The reason why the state detectors and the Viterbi decoders are constructed by two channels is to apply a Viterbi algorithm such that PR4(+1, 0, −1) data output from a channel demodulator
120
is converted into PR(+1, −1) data, to satisfy conditions that “0” or “−1” is read out after “+1” and “+1” is never read out, and that “0” or “+1” is read out after “−1” and “−1” is never read out.
Further, the DVCR having the PR4 channel shown in
FIG. 1
may perform decoding of data using the maximum likelihood decoding algorithm such as Viterbi decoding algorithm, which is referred to as a PRML system.
FIG. 2
is a block diagram of a digital recording/reproducing system having an EPR4(1, 1, −1, −1) channel having the simplest structure among E
n
PR4 channels. A detailed explanation of the same elements corresponding to those shown in
FIG. 1
will be omitted herein. A typical example of the digital recording/reproducing apparatus having the EPR4 channel is a hard disk driver.
In
FIG. 2
, compared to the PR4 system shown in
FIG. 1
, a precoder
208
includes one more delay
214
to have a 1/(1+D)
2
characteristic, in which the precoder
208
is called an EPR4(1, 1, −1, −1) precoder. Since a recording system includes three delays
206
,
212
and
214
, a reproducing system requires 2
3
8-state Viterbi decoders
250
through
264
and eight state detectors
234
through
248
. Also, a channel demodulator
222
includes an adder
228
and two delays
224
and
226
to have a (1+D)
2
characteristic, in correspondence with the precoder
208
having the 1/(1+D)
2
characteristic. In
FIG. 2
, “SD” refers to a state detector and “VD” refers to a Viterbi decoder. A driving clock CK output from a timing detector
268
is supplied to a demultiplexer
232
, first through eighth Viterbi decoders
250
through
264
and a multiplexer
266
. Reference numerals
218
and
220
denote an amplifier and an equalizer, respectively.
FIG. 3
is a block diagram of a digital recording/reproducing apparatus having an E
n
PR4 channel. A channel demodulator
312
corresponding to a precoder
304
having a 1/(1+D)
n+1
characteristic is constructed to have a (1+D)
n+1
characteristic. A maximum likelihood decoder
314
includes 2
n+2
Viterbi decoders, 2
n+2
state detectors, a demultiplexer for demultiplexing outputs of the channel demodulator
312
to output to the 2
n+2
state detectors, and a multiplexer for multiplexing outputs of the 2
n+2
Viterbi decoders to output decoded data. In other words, each 2
n+2
of the state detectors and the Viterbi decoders are constructed in parallel. Demodulated data are demultiplexed into 2
n+2
channels, independently decoded by the Viterbi decoders constructed to correspond to the respective channels and then multiplexed again. This is for applying a Viterbi algorithm by separating the E
n
PR4 signals of the channel demodulator
312
into PR(1, −1) signals to satisfy conditions that “0” or “−1” is read after “+1” and “+1” is never read, and that “0” or “+1” is read after “−1” and “−1” is never read.
An EPR4 system and an E
2
PR4 system are more resistant to noise than a PR4 system and an EPR4 system, respectively, and signal bands thereof are reduced. Thus, the recording density of a channel band is increased. However, the aperture ratio of an eye pattern is decreased and the hardware becomes complex. In other words, the conventional PR4 system requires four maximum likelihood decoders constructed in parallel (two for a DVCR), the EPR4 system requires eight maximum likelihood decoders constructed in parallel, and the E
n
PR4 system requires 2
n+2
maximum likelihood decoders constructed in parallel. Thus, the hardware burden becomes greatly increased.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a data decoding apparatus which can greatly decrease hardware size by decoding data using a maximum likelihood decoder having a single channel while maintaining the performance of a PR4 system in view of noise, in a digital recording/reproducing apparatus having a PR4 channel.
It is a second object of the present invention to provide a data decoding apparatus which can greatly decrease the hardware size by decoding data using a maximum likelihood decoder having a single channel while maintaining the performance of an E
n
PR4 system in view of noise, in a digital recording/reproducing apparatus having an E
n
PR4 channel.
It is a third object of the present invention to provide a data decoding apparatus for selectively decoding data into a PR4 mode or an E
n
PR4 mode, in a digital recording/reprodu
Jeon Jin-Kyu
Soichi Iwamura
Corrielus Jean B.
Pham Chi H.
Samsung Electronics Co,. Ltd.
Sughrue Mion Zinn Macpeak & Seas, PLLC
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