Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-04-20
2002-06-04
Gordon, Paul P. (Department: 2786)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S756000
Reexamination Certificate
active
06401228
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a data decoding apparatus and method and data reproduction apparatus, and more particularly, is applicable to such apparatus that reproduces moving pictures digitalized and recorded in a disc.
2. Description of the Related Art
There have been discs on which moving pictures are digitalized and recorded at a variable rate according to, for example, the moving pictures expert group (MPEG) standard.
The MPEG specifies three types of pictures for picture data: I pictures (Intra-Pictures) that are intra-frame coded pictures, P pictures (Predictive-Pictures) that are inter-frame forward predictive coded pictures, and B pictures (Bidirectionally predictive-Pictures) that are bidirectionally predictive coded pictures. These three types of pictures form a group of pictures (GOP).
Although the MPEG standard is also applied to voice data, for example, the additive transform acoustic coding (ATAC) is also used to digitalize and compressing-code voice data. ATRAC is a trademark.
FIG. 1
shows a data decoding apparatus
1
for reproducing data recorded on a disc at a variable rate. The data decoding apparatus
1
uses a pickup
3
to irradiate an optical disc
2
with laser beams to reproduce data recorded thereon from reflected beams. A reproduced signal S
1
output from the pickup
3
is input to and demodulated in a demodulating circuit
6
in a decoding circuit system
5
controlled by a system controller
4
. The data, demodulated by the demodulating circuit
6
, is input to an error correction code (ECC) circuit
8
via a sector detection circuit
7
, in which error detection's and corrections are carried out.
If the sector detection circuit
7
has not properly detected the sector numbers or addresses assigned to the sectors of the optical disc
2
, a sector number error signal is output to a track jump determination circuit
9
. If uncorrectable data has been found, the ECC circuit
8
outputs an error signal to the track jump determination circuit
9
. Error-corrected data is sent out from the ECC circuit
8
to a ring buffer memory
10
and recorded thereon.
A ring buffer control circuit
11
then reads the address of each sector from the output from the sector detection circuit
7
, and specifies the write address (hereinafter, referred to as a write pointer WP) on the ring buffer memory
10
which corresponds to the first address.
The ring buffer control circuit
11
, controlled by the system controller
4
, specifies a read address (hereinafter, referred to as a read pointer RP) for the data that has been written to the ring buffer memory
10
, based on a code request signal R
10
from a multiplexed data separation circuit
13
located beyond the ring buffer control circuit, and reads data from the read pointer RP to supply it to the multiplexed data separation circuit
13
.
A header separation circuit
14
in the multiplexed data separation circuit
13
separates a pack header and a packet header from the data supplied from the ring buffer memory
10
, and supplies them to a separation circuit control circuit
15
. The separation circuit control circuit
15
sequentially and cyclically switches and connects the input terminal G and output terminals (switched terminals) H
1
and H
2
of a switching circuit
16
according to the stream ID (identifier) information of the packet header supplied from the header separation circuit
11
, and correctly separates the time-division-multiplexed data to supply it to a code buffer.
A video code buffer
17
then generates a code request R
1
to the multiplexed data separation circuit
13
using the remaining amount of internal code buffer. The video code buffer
17
stores received data. It also receives a code request R
1
from a video decoder
18
and outputs the data therein. The video decoder
18
reproduces a video signal from the data supplied and outputs it from its output OUT
1
.
An audio code buffer
19
generates a code request R
2
to the multiplexed data separation circuit
13
using the remaining amount of internal code buffer. The audio code buffer
19
stores received data. It also receives a code request R
2
from an audio decoder
20
and outputs the data therein. The audio decoder
20
reproduces an audio signal from the data supplied and outputs it from its output OUT
2
.
As described above, the video decoder
18
requests data from the video code buffer
17
, the video code buffer
17
requests data from the multiplexed data separation circuit
13
, and the multiplexed data separation circuit
13
requests data from the ring buffer control circuit
11
.
In this case, the data flows from the ring buffer memory
10
in the direction opposite to that of the requests.
Data decoding carried out by the demodulating circuit system
5
is described. The reproduced signal S
1
read from the disc
2
is converted into a binary signal by the demodulating circuit
6
using RF processing. Then a rough servomechanism acts on the reproduced signal S
1
based on the measurement result of the mark length of the signal S
1
. When the sector detection circuit
7
, as an interface to the system controller
4
, detects an EFM+ sync header, a PLL (Phase Locked Loop) servomechanism acts on the sync header. When several sync headers are subsequently and continuously detected, data S
2
, which has been EFM+-demodulated, is deinterleaved.
As shown in
FIG. 2
, the EFM+-demodulated data S
2
is sent out to the ECC circuit
8
, stored in a RAM
24
, and then ECC-decoded by ECC decoders
25
,
27
, and
29
for three sequences C11 (the first C1 sequence), C2, and C12 (the second C1 sequence) including C1/C2 convolutional Reed and Solomon codes (CIRC Plus).
The ECC circuit
8
carries out ECC-decoding by, for example, writing the EFM+-demodulated data S
2
to the RAM
24
in the order of 00, 01, . . . , A8, and A9 (EFM+ Write) and once two frames of EFM+ demodulated data has been stored in the RAM
24
, transferring the data in frame
1
to the ECC decoder
25
in the order of 00′, 02′, . . . , A8′, 01, 03, . . . , A9 to ECC-decode the deinterleaved C1 sequence of data, as shown in FIG.
3
.
Errors are corrected by reading the error positions and correction patterns from the ECC decoder
25
, reading the erroneous data from the RAM
24
(C1 read), exclusively logically adding this data to the correction patterns, and writing the resultant data back to the RAM
26
(C1 Write), as shown in FIG.
4
. The ECC decoder
25
ECC-decodes the C1 sequence of data over a C2 code sequence length.
Once the C1 sequence data has been ECC-decoded over a C2 code sequence length, the C2 sequence of data can then be ECC-decoded. The data on the RAM
26
is read on the order of 00′, 01′, 02′, 03′, . . . , A9 ′(C2 read), and the ECC decoder
27
ECC-decodes this C2 sequence of data. An uncorrectable error flag for each frame can be transferred to the next ECC decoder in synchronism with the data so as to execute erasure corrections. The C1 uncorrectable error flag is used to apply an erasure correction to the C2 sequence of data. The error correction operation is as in C1.
As shown in
FIG. 5
, once the results of the ECC-decoding of the C2 sequence of data have been written to the RAM
28
(C2 Write) and the C2 sequence of data has been ECC-decoded over a C1 code sequence length, the C12 sequence of data can then be ECC-decoded, and the ECC-decoder
29
ECC-decodes the C12 sequence of data read in the order of 00′, 01, 02, 03, . . . , A9 (C12 read).
The C2 uncorrectable error flag is used to apply an erasure correction to the C12 sequence of data. Once the error correction of the C12 data has been finished, the results of the ECC-decoding of the C12 sequence of data is written to a RAM
30
in the order of 00, 01, 02, 03, . . . , A9, as shown in FIG.
6
. The decoded ECC C11, C2, and C12 sequence of data is thus stored in the RAM
30
and then read in the order of 00, 01, 02, 03, . . . , A9 (OUT read). T
Ichikawa Takahiro
Kimura Satoru
Sato Shigeharu
Yasuda Kazuhiro
Frommer William S.
Frommer & Lawrence & Haug LLP
Gordon Paul P.
Smid Dennis M.
Sony Corporation
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