Data decoder and method of decoding data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S776000, C709S236000, C370S509000, C398S154000

Reexamination Certificate

active

07039849

ABSTRACT:
A detecting circuit detects a boundary in a bit stream which is coded in compliance with a predetermined rule. The boundary is a point at which discontinuity of reproduction time occurs. An inverting circuit inverts a specific bit in a header of a succeeding bit stream immediately subsequent to the boundary, in response to the detection of the boundary by the detecting circuit. The boundary can thus be detected easily by simply monitoring the specific bit, for example, in outputting the decoded bit streams. This consequently facilitates synchronous management and the like of the bit streams. The specific bit is included in the bit stream. Thus, detecting the specific bit allows simple and accurate detection of the boundary at which discontinuity of the reproduction time occurs.

REFERENCES:
patent: 6298387 (2001-10-01), Prasad et al.
Lampow-Maundy et al. ‘Frame synchronization in guided scrambling line codes,’ IEEE Transactions on Communications, Dec. 2000, vol.: 48 , Issue: 12 On page(s): 1992-1996.
Fair et al. ‘Metric based node synchronization of the Viterbi decoder,’IEEE 1997 Canadian Conference on Electrical and Computer Engineering, May 25-28, 1997 vol.: 1, page(s): 78-82 vol. 1.
Sharp et al. ‘Detection of variable message lengths for NATO Improved Link Eleven using CRC codes,’ Military Communications Conference, 1991. MILCOM '91, Conference Record, ‘Military Communications in a Changing World’., IEEE; Nov. 4-7, 1991; page(s): 910-4.

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