Data correcting hierarchical integrated circuit layout...

Details Data correcting hierarchical integrated circuit layout... Data correcting hierarchical integrated circuit layout...

2008-04-25

2010-11-30

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07844938

ABSTRACT:
A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.

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Search Report and Written Opinion of FIS920080002PCT .International Serial No. PCT/US09/39703.

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