Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1999-02-02
2002-07-23
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S539000, C345S042000, C345S063000
Reexamination Certificate
active
06424349
ABSTRACT:
This application claims the benefit of Korean patent application No. 12604/1998 filed Apr. 9, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a data controller for a display panel, and more particularly, to an improved data controller for a display panel that converts inputted video data to pulse stream data and outputs the pulse stream data to a plasma display panel driver.
2. Discussion of the Related Art
In order to display a gray scale video on a display device, such as a plasma display panel, video data must be outputted by a data controller as bit frame data. For example, 8-bit video data is divided into a total of 8 frames. Then, the 8 frames, that is, 8-bit frame data, 7-bit frame data, 6-bit frame data, 5-bit frame data, 4-bit frame data, 3-bit frame data, 2-bit frame data, and 1-bit frame data, must be inputted to the plasma display panel by the data controller.
However, the video data (R, G, B) inputted from an external system (not illustrated) are inputted in pixel units (pixel format), and thus the plasma display panel driver requires a data controller for converting the video data from the pixel format to the bit frame data format.
FIG. 1
illustrates a related art data controller. As shown in
FIG. 1
, the related art data controller includes a first memory
10
for storing inputted video data, a second memory
20
for storing next inputted data, and a control unit
30
for controlling the first and second memories
10
,
20
to either store the video data or output the previously stored video data.
The operation of the related art data controller will now be described with reference to FIG.
1
.
Pursuant to an inputted first clock signal CLK, the control unit
30
outputs a second clock signal CLK′ and respective control signals I/
01
, I/
02
to the first memory
10
and the second memory
20
.
Then, the first memory
10
and the second memory
20
are synchronized by the second clock signal CLK′ and either store the inputted video data or output the previously stored video data in accordance with the control signals I/
01
, I/
02
, respectively.
The first memory
10
and the second memory
20
are alternately operated. That is, pursuant to the control signals I/
01
, I/
02
, the first memory
10
stores the video data, and at the same time the second memory
20
outputs the video data. Therefore, the first memory
10
and the second memory
20
convert the inputted video data from the pixel format to the bit frame data format, and output the video data in response to commands from the control unit
30
.
The bit frame data outputted from the first and second memories
10
,
20
are inputted to the plasma display panel. Then, as illustrated in
FIG. 2
, the bit frame data is displayed in different sections and represents a gray scale.
At this time, sustain-discharge periods (A, B, C, D, E, F, G, H) are an 8th bit sustain-discharge period, a 7th sustain-discharge period, a 6th sustain-discharge period, a 5th sustain-discharge period, a 4th sustain-discharge period, a 3rd sustain-discharge period, a 2nd sustain-discharge period and a 1st sustain-discharge period. The ratio of the sustain-discharge periods (A, B, C, D, E, F, G, H) are 128:64:32:16:8:4:2:1. Addressing periods (I, J, K, L, M, N, O, P) mean bit frames 8 (MSB or most significant bit), 7, 6, 5, 4, 3, 2, 1 (LSB or least significant bit) respectively.
In the related art data controller, when the inputted data has 8 bits, the length of the sustain-discharge period for the most significant bit (MSB) is equal to the sum of the sustain-discharge periods for the other bits as shown in FIG.
2
. Also, a half of the frame is turned on, and the other half is turned off. In addition, when data such as 127, 128, 127, . . . are sequentially inputted to one pixel, the bit frame data outputted from a data conversion unit are represented on the time axis, as illustrated in FIG.
3
.
Here, video data ‘127’ and ‘128’ become ‘01111111’ and ‘10000000’, . . . respectively, in binary. The bit frame data (Q, R, S) shown in
FIG. 3
are ‘127’, ‘128’ and ‘127’ represented in binary form.
When a plurality of bit frames are thus displayed, although a 60 Hz video is displayed, a noticeable flicker results as if 30 Hz video is displaced. In other words, a flicker for a continually displayed specific color is noticeable to a user.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a data controller for a display panel that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an improved data controller for a display panel that prevents flicker for a specific color and displays a gray scale with a simple on/off function.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect of the present invention there is provided a data controller for a display panel including a first memory for storing video data, a second memory for storing next video data, a control unit for controlling the first memory and the second memory for one of storing and outputting the video data stored in at least one of the first and second memories, and a data converter for converting the video data outputted from the at least one of first and second memories to pulse stream data.
In another aspect of the present invention there is provided a data controller for a display panel including a first memory for storing video data, a second memory for storing next video data, a control unit for controlling the first memory and the second memory for one of storing and outputting the video data stored in at least one of the first and second memories, and a data converter for converting the video data outputted from the at least one of the first and second memories to pulse stream data, wherein the data converter includes a random number generator for generating random number signals in response to a clock signal outputted from the control unit, and first, second and third comparators for comparing the random number signals and the video data outputted from the at least one of the first memory and the second memory, and outputting the pulse stream data, wherein each of the first, second and third comparators are multiple bit comparators, wherein the random number signals are applied to plus terminals of the first, second and third comparators, wherein the video data output from the at least one of the first memory and the second memory is applied to minus terminals of the first, second and third comparators, and wherein the data converter and the control unit are integrally formed.
In another aspect of the present invention there is provided a data controller for a display panel including a first memory for storing video data, a second memory for storing next video data, a control unit for controlling the first memory and the second memory for one of storing and outputting the video data stored in at least one of the first and second memories, and a data converter for converting the video data outputted from the at least one of the first and second memories to pulse stream data, wherein the data converter includes a random number generator for generating random number signals in response to a clock signal outputted from the control unit, and first, second and third comparators for comparing the random number signals and the video data outputted from the at least one of the first memory and the second memory, and outputting the pulse stream data, wherein
Chauhan Ulka J.
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
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