Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-09-19
2004-06-29
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S147000, C711S163000, C711S153000, C711S152000
Reexamination Certificate
active
06757786
ABSTRACT:
The present invention relates to a data consistency memory management system and method, as well as to a corresponding multiprocessor network.
BACKGROUND OF THE INVENTION
Fast processors clocked at speeds of more than 100 MHz generally use cache memories, also referred to simply as caches, to be able to operate efficiently. Such a cache duplicates some of the data present in main memory (such as a synchronous access memory or SDRAM), over to a memory offering a much faster access time than the latter. In a conventional system, the cache is limited in size for reasons of cost and bulk, and only a small part of the main memory lies in the cache at a given time. In improved systems, several levels of caches are cascaded, each level being specified by the time to access a data item and by its storage capacity. Customarily, the first cache level allows access to data at the speed of the processor.
A difficulty appears in a so-called multimaster environment, where several processors use the same main memory. Specifically, data consistency must then be ensured between the main memory and the cache or the caches, both in read and write mode, with no risk of overwriting information.
This is especially salient in a so-called “write-back” cache mode. In such a mode, writes are performed by the associated processor directly to the cache and are carried over into main memory only during operations for updating the data of the cache (dumping or flush), whereas in a so-called “write-through” cache mode, writes are on the contrary carried over in real time from the cache to the main memory. The write-back mode is distinguished by its efficiency, since it requires a smaller frequency of transfers between the cache and the main memory. However, the consistency of the data between the cache and the main memory is not ensured at all times. The reading of data from the main memory by a processor other than that associated with the cache currently being used therefore poses a problem.
Another problem, existing in both write-back and write-through modes, relates to the writing of data in main memory by a processor, when a cache is currently being used by another processor. When transferring information from the cache to the main memory, the data registered in the latter memory is in fact at risk of being overwritten.
Several solutions are currently used to remedy these difficulties, relying on hardware or software means. They guarantee that at any instant, memory data belongs to just one of the masters. The hardware means guaranteeing the consistency of data (such as the so-called “snoop” technique) customarily implement complex solutions, in which any master accessing a data item in main memory must be sure that a subassembly furnished with a cache does not possess the data item before manipulating it. If such is the case, the data item is made available to the main memory or to the master by a memory write mechanism. In addition to their complexity and cost of installation, these systems require that passbands be allocated to the processors. They penalize the processing times through holdups.
The software means guaranteeing the consistency of data customarily compel segmented management of the data, that is to say management organized in such a way that each master is furnished with one or more dedicated memory spaces and with a shareable memory area. The memory spaces dedicated to a master can be accessed only by the caches associated with this master, the data not being shared therein with other masters, whilst the shareable memory area cannot be accessed by the caches and serves as data exchange area. Another software means of ensuring the consistency of data implements specific processor instructions for managing caches, capable of manipulating cache data blocks so as to ensure the consistency of this data between caches and main memory. This means also compels data management organized so as to take account of the size of the data blocks manipulated by these instructions, in such a way as to preclude different masters from accessing the same data blocks through write operations (risk of overwriting).
In all cases these software techniques require precise synchronization and an initial overall design incorporating constraints related to the multiprocessor operation of the system. Moreover, they require that there be made available in each of the processors, management programming adapted to the exchanges of data between caches and the main memory within all the processors.
SUMMARY OF THE INVENTION
The present invention relates to a system for memory management of data consistency relating to a main memory accessible by at least two processors, making it possible to ensure consistency between caches of one or more processors and the main memory. The memory management system of the invention can ensure this consistency in read and/or write mode in the main memory, and permits reliable, economic and easy installation and implementation, in regard to the existing methods. In particular, it offers these advantages when the multiprocessor operation results from an upgrade of a monoprocessor system. Moreover, it can yield high processing speeds, as compared with the known hardware means.
The invention also pertains to a multiprocessor network incorporating a memory management system according to the invention and to a data consistency memory management method, having the advantages cited above.
It applies in particular to the audiovisual field, especially for digital decoders.
To this end, the subject of the invention is a system for memory management of data consistency relating to a main memory accessible by at least two processors. At least one of these processors is furnished with one or more cache memories associated with at least one area of the main memory, referred to as the assignment area of this processor. The management system comprises:
an assembly for management of access of the processors to at least one common area of the main memory, referred to as the exchanges area,
one or more copy modules respectively associated with one or more of the processors furnished with at least one cache memory, hereinafter designated as first processors; each of these copy modules is capable of performing a data copy between a memory workspace consisting of one of the cache memories and/or the assignment area of the associated first processor, on the one hand, and the exchanges area, on the other hand,
and one or more data transfer modules, associated respectively with one or more second processors capable of exchanging data with the first processors; each of these transfer modules is intended for transferring data between the exchanges area and the associated second processor.
According to the invention, the consistency management system also comprises triggering means controlled by the second processors, capable of triggering the copy modules of the first processors and the transfer modules of the second processors when the first processors submit requests involving transfers of data between the memory workspaces of the first processors and the second processors.
The expressions “copy module” and “transfer module” are not intended to be understood as specified physical objects, but as functional entities which may for example be grouped together and integrated physically into one or more hardware supports, or on the contrary each dispersed in several supports.
The expression “data” may be understood equally well, in particular, as references to data in memory and as command identifiers.
The memory workspace used by the copy module is that active during the reading or writing of data. Thus, when the data exchanged with a first processor is present in cache, it is the latter which serves as point of departure in read mode and as point of arrival in write mode. When conversely the targeted data is in a memory space of the assignment area which is not utilized in cache, the data is read or written directly from or to this assignment area of the main memory. In all cases the first processor is itself capa
Metayer Jean-Jacques
Steyer Jean-Marie
McLean-Mayo Kimberly
Shedd Robert D.
Thomson Licensing S.A.
Tripoli Joseph S.
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