Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Patent
1997-05-09
1999-06-22
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
714711, 714718, 365201, G11C 2900
Patent
active
059139285
ABSTRACT:
A method and circuit for testing cells in a memory device is disclosed. Data is written to the cells and then the cells are read in groups. For example, groups of four cells are read together. Output bits of the four cells are compressed in a compression circuit to generate compressed data, and the compressed data is checked to determine if one or more of the four cells was defective and produced an incorrect output bit. If one of the cells was defective, each cell is read in a sequence and its output bit is tested to determine which of the four cells is defective. The defective cell is replaced with a redundant cell.
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Micro)n Technology, Inc.
Nguyen Hoa T.
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