Data compression read mode for memory testing

Details Data compression read mode for memory testing Data compression read mode for memory testing

2007-08-07

2007-08-07

Kerveros, James C (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

10696971

ABSTRACT:
A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first series combination compares the values in the predetermined bit position to determine if they are all a logical zero. A second series combination of bit match circuits compares the same predetermined bit position in the data words. The second series combination compares the values to determine if they are all a logical one. If either condition is true, the value of the bit is output through an output buffer. If both conditions are false, the output buffer is placed in a high impedance state to indicate an error condition exists in that bit position.

REFERENCES:
patent: 5966388 (1999-10-01), Wright et al.
patent: 6016561 (2000-01-01), Roohparvar et al.
patent: 6032274 (2000-02-01), Manning
patent: 6550026 (2003-04-01), Wright et al.

Affiliated with

Also associated with

Rating

Data compression read mode for memory testing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data compression read mode for memory testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data compression read mode for memory testing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3870981