Data compression circuit and method for testing memory devices

Details Data compression circuit and method for testing memory devices Data compression circuit and method for testing memory devices

2006-01-31

2006-01-31

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S189070, C714S718000

Reissue Patent

active

RE038956

ABSTRACT:
A test circuit detects defective memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data. A control circuit is coupled to the test mode terminal, the error detection circuit, and the memory cells. The control circuit is operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.

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