Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-02-21
1999-08-10
Ray, Gopal C.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395309, 711202, G06F 300, G06F 1300, G06F 1202
Patent
active
059371706
ABSTRACT:
A computer system includes a microprocessor running in big-endian mode and both big-endian and little-endian peripherals, including a little-endian SCSI controller that controls a hard disk. When a program calls for a data transfer between the hard disk and random-access memory, the operating system determines a peripheral-accessible memory address range for the data transfer. A bridge driver intercepts this range and determines whether or not the data needs to be swizzled to take into account differing endianness. The determination is encoded into the most significant bit of a processor-assertable address range, and the bits of lesser significance indicate the peripheral-accessible address range. The processor-assertable address range is conveyed to the SCSI controller originating the data transfer. A communications bridge extracts the processor-assertable address from the origination information from the SCSI controller. The bridge maps the processor-assertable address range to a product space of peripheral-accessible addresses and a command set. The mapping indicates the peripheral-accessible address range intended by the operating system and an indication that swizzling need to be performed. In addition, the second most significant bit of the processor-assertable address is used to indicate that cache snooping is required for the transfer. The invention efficiently allows peripherals designed for one endian environment to work in a different endian environment.
REFERENCES:
patent: 4315310 (1982-02-01), Bayliss et al.
patent: 4535404 (1985-08-01), Skenk
patent: 5548746 (1996-08-01), Carpenter et al.
patent: 5640528 (1997-06-01), Harney et al.
patent: 5699542 (1997-12-01), Mehta et al.
Gillig, James R. "Endian-Neutral Software, Part 1" Dr. Dobb's Journal, Oct., 1994, pp. 62, 64, 68-70.
James, David V., "Multiplexed Buses: The Endian Wars Continue", IEEE, Jun. 1990, pp. 9-21.
Anderson Clifton L.
Ray Gopal C.
VLSI Technology Inc.
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