Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-01-26
2002-02-05
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S158000, C710S034000, C710S039000, C710S041000, C710S116000, C710S120000
Reexamination Certificate
active
06345345
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to data communications, and more particularly, to a system for arbitrating access to a system memory.
BACKGROUND ART
In a data communications device, buffer memories are provided between a system memory interface and a media interface for temporarily storing data transferred between a system memory and a communications network. In particular, a receive buffer memory accumulates receive data supplied from the network, before transferring the data to the system memory, whereas a transmit buffer memory is involved in transferring transmit data from the system memory to the network.
Conventionally, the receive buffer memory accesses the system memory to transfer receive data, when amount of accumulated receive data exceeds a threshold value established to handle data traffic. The transmit buffer memory accesses the system memory to retrieve transmit data, when available buffer capacity exceeds a threshold level sufficient for holding the transmit data. However, the receive and transmit buffer memories may request access to the system memory at the same time. As a result, a collision may occur.
Thus, it would be desirable to provide a system for performing arbitration between receive and transmit buffer memories requesting access to a system memory at the same time.
Also, it would be desirable to dynamically program the arbitration system in accordance with data traffic conditions, in order to make a communications system more efficient.
SUMMARY OF THE INVENTION
Accordingly, the advantage of the present invention is in providing a system for arbitrating between receive and transmit buffer memories requesting access to a system memory.
Another advantage of the present invention is in providing an arbitration system which may be dynamically programmed in accordance with data traffic conditions.
These and other advantages of the present invention are achieved at least in part by providing a data communications device coupled to a system memory and having a receive buffer memory for temporarily storing receive data supplied from a communications network, and a transmit buffer memory for temporarily storing transmit data retrieved from the system memory. A memory management circuit is coupled to the receive and transmit buffer memories for managing transmit data transfers from the system memory to the transmit buffer memory and receive data transfers from the receive buffer memory to the system memory. An arbitration circuit is provided for arbitrating access to the system memory in response to access requests.
In accordance with one aspect of the present invention, the memory management circuit may comprise a transmit transfer control register having transmit data transfer control values for limiting the number of the transmit data transfers in each period of access to the system memory granted by the arbitration circuit. The transmit data transfer control values may be dynamically programmed in accordance with data traffic. Alternatively, the transmit data transfer control values may be preprogrammed in accordance with application of the communications device, for example, depending on whether the device is a network client or a file server.
The transmit data transfer control values may include a transmit transfer maximum value that limits the maximum number of transmit data transfers in one period of access to the system memory. Also, the transmit data transfer control values may include a transmit transfer limit value that limits the number of transmit data transfers in one period of access to the system memory, when access to the system memory is also requested for providing receive data transfers.
In accordance with another aspect of the invention, the memory management circuit may comprise a receive transfer control register having receive data transfer control values for limiting the number of the receive data transfers in one period of access to the system memory granted by the arbitration circuit. The receive data transfer control values may be dynamically programmed in accordance with data traffic, or may be preprogrammed in accordance with application of the communications device.
The receive data transfer control values may include a receive transfer maximum value that limits the maximum number of receive data transfers in one period of access to the system memory. Also, the receive data transfer control values may include a receive transfer limit value that limits the number of transmit data transfers in one period of access to the system memory, when access to the system memory is also requested for providing the transmit data transfers.
In accordance with a preferred embodiment of the invention, the system memory may be coupled to the receive and transmit buffer memories via a bus, such as a peripheral component interconnect (PCI) bus. The arbitration circuit arbitrates access to the bus.
In accordance with a further aspect of the invention, the access requests supplied to the arbitration circuit include a transmit data request to read transmit data from the system memory to the transmit buffer memory, a receive data request to write receive data from the receive buffer memory to the system memory, a receive descriptor request to read a receive descriptor from the system memory, a transmit descriptor request to read a transmit descriptor from the system memory, a receive status request and a transmit status request to write receive status information and transmit status information, respectively, to the system memory.
In accordance with another aspect of the invention, the receive descriptor request has the highest priority when tile arbitration circuit provides access arbitration. File transmit descriptor request has the next priority after the receive descriptor request.
In accordance with a further aspect of the invention, the receive data request may have priority over the transmit data request when the arbitration circuit provides access arbitration immediately after reset of the communications device.
During normal operations, the transmit data request may have priority over the receive data request if the last access to the system memory before performing access arbitration was provided to write the receive data. However, the receive data request may have priority over the transmit data request if the last access to the system memory was performed to read the transmit data.
In accordance with a method of the present invention the following steps are carried out to arbitrate access to a bus between a system memory and transmit and receive buffer memories:
providing a transmit data request to access the bus for reading transmit data from the system memory to the transmit buffer memory,
providing a receive data request to access the bus for writing receive data from tile receive buffer memory to the system memory, and
providing arbitration between the transmit data request and the receive data request in accordance with a priority scheme.
Further, the method of the present invention may include a step of programming transmit transfer control values for limiting number of transmit data transfers allowed in one period of access to the bus, and a step of programming receive transfer control values for limiting number of receive data transfers allowed in one period of access to the bus.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 4875206 (1989-10-01), Nichols et al.
patent: 5619651 (1997-04-01), Young
pat
Kuo Jerry
Yu Ching
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