Data communication system with an SPI bus having a plurality...

Details Data communication system with an SPI bus having a plurality... Data communication system with an SPI bus having a plurality...

2007-06-05

2007-06-05

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S022000, C375S354000, C701S001000

Reexamination Certificate

active

11016769

ABSTRACT:
A data communication system includes a master device, a plurality of slave devices, at least either a data transmission bus which connects the master device to a plurality of slave devices to transfer data from the master device to the slave devices in synchronism with a synchronous clock signal or a data reception bus over which the master device receives data from the slave devices in synchronism with a synchronous clock signal, and Chip Select signal lines which one-to-one connect the master device to the slave devices. The data communication system also includes communication drivers for setting a physical protocol of each slave device and a communication manager to arbitrate serial communications between the master device and the slave devices. The communication manager arbitrates serial communications to slave devices by their proper physical protocols. Communication protocols such as baud rates, clock polarities, and clock phases are switched by asserted Chip Select signal lines.

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“High performance, energy efficient master-slave flip-flops circuits” by Ko et al. (abstract only) Publication Date: Oct. 9-11, 1995.
“Power is Control” MPC 555 User's Manual—Revised .095 Jan. 2001 (Motorola). Overview of Chapter 14—pp. 14-1 through 14-76.

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