Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-11-14
2006-11-14
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S029000, C710S311000
Reexamination Certificate
active
07136954
ABSTRACT:
A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.
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Check Mark Anthony
Drerup Bernard Charles
Grassi Michael
Auve Glenn A.
Truelson Roy W.
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