Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-01-05
2001-01-23
Ray, Gopal C. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C341S126000
Reexamination Certificate
active
06178476
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to an integrated digital processor and memory device and more specifically to a method and apparatus for serial data processing, including an integrated processor and serial memory device for uses including as an integral part of a data communication interface and digital audio system.
BACKGROUND OF THE INVENTION
Data processors are used for processing vast quantities of information very rapidly. Integrated circuit microprocessor technology improvements have progressively increased the processing speed of those devices. Generally a microprocessor and a separate integrated circuit random access memory device are combined into a microcomputer system as a practical operating arrangement. Integrated circuit random access memory devices generally fall into one of two categories.
One category of random access memory includes static storage cells. Such static random access memory (SRAM) devices are designed to operate at very fast speeds and can readily operate as fast as contemporary integrated circuit microprocessors. Although they operate fast enough to keep up with the microprocessor, the static random access memory devices are relatively expensive to produce. Their high cost causes microcomputer system designers to look for lower cost memory alternatives to minimize microcomputer system cost.
A second category of random access memory devices includes dynamic storage cells. Dynamic random access memory (DRAM) devices are designed to be very inexpensive by comparison to the cost of static random access memory devices. Although they have a very attractive low cost, dynamic random access memory devices generally operate significantly slower than the previously mentioned static random access memory devices. Their speed is slow enough that microcomputer system designers look for other devices and special arrangements to speed up the dynamic memory function so that the microcomputer system can operate at faster and faster speeds.
One recently proposed solution to the memory speed and cost trade-off is an arrangement known as a smart memory. A smart memory is an integrated circuit device that includes both a processing core and a memory array. The processing core is operable to execute instructions stored in the memory array and to communicate data with the memory array. External connections to the smart memory are arranged so that the smart memory functions as a standard random access memory device with respect to internal devices.
Known smart memory devices are limited in the types of paths through which data can flow within the device. Such limited types of data paths reduce the flexibility of accessing data within the smart memory devices and of processing that data and other data.
SUMMARY OF THE INVENTION
These and other problems are resolved by an integrated circuit serial data processor device that includes a digital processor, a memory controller interconnected with the digital processor, and a dynamic serial access memory interconnected with the memory controller. A first data selection circuit sends serial data from either a data-in terminal, the serial memory, or the digital processor to the serial memory. A second data selection circuit sends serial data from either the data-in terminal, the serial memory, or the digital signal processor to a data-out terminal.
A data communication interface includes a serial data source arranged with a first bus for carrying serial data to a data-in terminal of a serial data processor. A digital system is arranged with a second bus for carrying address signals, control signals, and data between the digital system and the serial data processor.
A digital audio processing system includes an audio medium arranged with a first bus for carrying serial data from the audio medium to a serial data-in terminal of a serial data processor. A controller is arranged with a second bus for carrying address signals, control signals, and serial data between the controller and the serial data processor and for carrying control signals to the audio medium. A conversion system is responsive to serial data from the serial data processor for producing audible sound.
REFERENCES:
patent: 4264954 (1981-04-01), Briggs et al.
patent: 4516201 (1985-05-01), Warren et al.
patent: 4713757 (1987-12-01), Davidson et al.
patent: 4728930 (1988-03-01), Grote et al.
patent: 4811007 (1989-03-01), Schreiber
patent: 5018188 (1991-05-01), Kowalski et al.
patent: 5020020 (1991-05-01), Pomfret et al.
patent: 5333199 (1994-07-01), Kuwasaki
patent: 5361374 (1994-11-01), Sasaki et al.
patent: 5537646 (1996-07-01), Buck et al.
patent: 5754803 (1998-05-01), Regis
patent: 0 446 721 A2 (1991-03-01), None
patent: 0 525 985 A2 (1992-06-01), None
Tony R. Martinez, Smart memory architecture and methods, 1990, pp. 145-162, FGCS, vol. 6.
Pawate, et al., Memory Based Digital Signal Processing, Texas Instruments Inc. , 1990, IEEE, V3.4, pp. 41-44.
Donaldson Richard L.
Hoel Carlton H.
Holland Robby T.
Ray Gopal C.
Texas Instruments Incorporated
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