Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Patent
1998-06-04
2000-08-15
Lee, Thomas C.
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
710 53, 710 55, 710 57, 709100, 709103, 711151, G06F 300
Patent
active
061050865
ABSTRACT:
A data communication circuit buffers data between a shared resource and a plurality of data communication interfaces through a plurality of respective first-in-first-out ("FIFO") buffers. The data is divided into multiple-bit data frames having a start and an end. The circuit maintains a priority level for each FIFO buffer and initializes the priority level of each FIFO buffer to a first priority level. The circuit passes bits of the multiple-bit data frames from the shared resource to respective ones of the FIFO buffers in a buffer order which is based on the priority level of each FIFO buffer. The circuit passes the bits from the FIFO buffers to the respective data communication interfaces and selectively increases the priority level of each FIFO buffer to a second, higher priority level as a function of a level the bits within the FIFO buffer and whether the end of at least one data frame is stored in the FIFO buffer.
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Doolittle Timothy N.
Holm Jeffrey J.
Lee Thomas C.
LSI Logic Corporation
Peeyton Tammara
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